Jeffrey R Swanson

US Patent:

20210117350, Apr 22, 2021

Filed:

Dec 25, 2020

Appl. No.:

17/134242

Inventors:

- Santa Clara CA, US
Robert G. Blankenship - Tacoma WA, US
Venkatraman Iyer - Austin TX, US
Jeff Willey - Timnath CO, US
Robert Beers - Hillsboro OR, US
Darren S. Jue - Sunnyvale CA, US
Arvind A. Kumar - Beaverton OR, US
Debendra Das Sharma - Saratoga CA, US
Jeffrey C. Swanson - Sunnyvale CA, US
Bahaa Fahim - Santa Clara CA, US
Vedaraman Geetha - Fremont CA, US
Aaron T. Spink - San Francisco CA, US
Fulvio Spagna - San Jose CA, US
Rahul R. Shah - Marlborough MA, US
Sitaraman V. Iyer - San Jose CA, US
William Harry Nale - Livermore CA, US
Abhishek Das - Portland OR, US
Simon P. Johnson - Beaverton OR, US
Yuvraj S. Dhillon - Hillsboro OR, US
Yen-Cheng Liu - Portland OR, US
Raj K. Ramanujan - Federal Way WA, US
Robert A. Maddox - Columbia SC, US
Herbert H. Hum - Portland OR, US
Ashish Gupta - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/22
H04L 12/933
G06F 12/0813
G06F 12/0815
G06F 12/0831
G06F 13/42
G06F 8/71
G06F 8/77
G06F 9/30
G06F 12/0806
G06F 9/46
G06F 13/40
G06F 9/445
G06F 1/3287
G06F 11/10
H04L 9/06
G06F 12/0808

Abstract:

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

US Patent:

20200356502, Nov 12, 2020

Filed:

Jul 23, 2020

Appl. No.:

16/937499

Inventors:

- Santa Clara CA, US
Robert G. Blankenship - Tacoma WA, US
Venkatraman Iyer - Austin TX, US
Jeff Willey - Timnath CO, US
Robert Beers - Hillsboro OR, US
Darren S. Jue - Sunnyvale CA, US
Arvind A. Kumar - Beaverton OR, US
Debendra Das Sharma - Saratoga CA, US
Jeffrey C. Swanson - Sunnyvale CA, US
Bahaa Fahim - Santa Clara CA, US
Vedaraman Geetha - Fremont CA, US
Aaron T. Spink - San Francisco CA, US
Fulvio Spagna - San Jose CA, US
Rahul R. Shah - Marlborough MA, US
Sitaraman V. Iyer - San Jose CA, US
William Harry Nale - Livermore CA, US
Abhishek Das - Portland OR, US
Simon P. Johnson - Beaverton OR, US
Yuvraj S. Dhillon - Hillsboro OR, US
Yen-Cheng Liu - Portland OR, US
Raj K. Ramanujan - Federal Way WA, US
Robert A. Maddox - Columbia SC, US
Herbert H. Hum - Portland OR, US
Ashish Gupta - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/22
H04L 12/933
G06F 12/0813
G06F 12/0815
G06F 12/0831
G06F 13/42
G06F 8/71
G06F 8/77
G06F 9/30
G06F 12/0806
G06F 9/46
G06F 13/40
G06F 9/445
G06F 1/3287
G06F 11/10
H04L 9/06
G06F 12/0808

Abstract:

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

US Patent:

20190391939, Dec 26, 2019

Filed:

Feb 25, 2019

Appl. No.:

16/285035

Inventors:

- Santa Clara CA, US
Robert G. Blankenship - Tacoma WA, US
Venkatraman Iyer - Austin TX, US
Jeff Willey - Timnath CO, US
Robert Beers - Hillsboro OR, US
Darren S. Jue - Sunnyvale CA, US
Arvind A. Kumar - Beaverton OR, US
Debendra Das Sharma - Saratoga CA, US
Jeffrey C. Swanson - Sunnyvale CA, US
Bahaa Fahim - Santa Clara CA, US
Vedaraman Geetha - Fremont CA, US
Aaron T. Spink - San Francisco CA, US
Fulvio Spagna - San Jose CA, US
Rahul R. Shah - Marlborough MA, US
Sitaraman V. Iyer - San Jose CA, US
William Harry Nale - Livermore CA, US
Abhishek Das - Portland OR, US
Simon P. Johnson - Beaverton OR, US
Yuvraj S. Dhillon - Hillsboro OR, US
Yen-Cheng Liu - Portland OR, US
Raj K. Ramanujan - Federal Way WA, US
Robert A. Maddox - Columbia SC, US
Herbert H. Hum - Portland OR, US
Ashish Gupta - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/22
G06F 12/0808
H04L 9/06
G06F 13/42
G06F 11/10
G06F 13/40
G06F 1/3287
G06F 9/445
G06F 9/46
G06F 12/0831
G06F 12/0806
G06F 9/30
G06F 8/77
G06F 8/71
G06F 12/0815
G06F 12/0813
H04L 12/933

Abstract:

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

US Patent:

20180196774, Jul 12, 2018

Filed:

Dec 22, 2017

Appl. No.:

15/851744

Inventors:

- Santa Clara CA, US
Robert Blankenship - Tacoma WA, US
Jeffrey Swanson - Sunnyvale CA, US

Assignee:

Intel Corporation - Santa Clar CA

International Classification:

G06F 13/42
H03M 13/09

Abstract:

A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.

US Patent:

20180143937, May 24, 2018

Filed:

Aug 31, 2017

Appl. No.:

15/692613

Inventors:

- Santa Clara CA, US
Robert G. Blankenship - Tacoma WA, US
Jeffrey C. Swanson - Sunnyvale CA, US
Robert J. Safranek - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/42
G06F 8/71
G06F 8/77
G06F 9/30
G06F 9/445
G06F 9/46
G06F 12/0806
G06F 12/0813
G06F 12/0815
G06F 12/0831
G06F 13/40
H04L 12/933

Abstract:

Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

US Patent:

20180011759, Jan 11, 2018

Filed:

Sep 15, 2017

Appl. No.:

15/706191

Inventors:

- Santa Clara CA, US
Robert G. Blankenship - Tacoma WA, US
Jeffrey C. Swanson - Sunnyvale CA, US
Robert J. Safranek - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/10
G06F 13/42
H03M 13/09

Abstract:

Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.

US Patent:

20170308497, Oct 26, 2017

Filed:

Dec 29, 2016

Appl. No.:

15/393518

Inventors:

- Santa Clara CA, US
Robert G. Blankenship - Tacoma WA, US
Jeffrey C. Swanson - Sunnyvale CA, US

Assignee:

Intel Corporation - Santa Clar CA

International Classification:

G06F 13/42
H03M 13/09
G06F 13/42

Abstract:

A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are to include a plurality of slots. Control messages can include, in some aspects, a viral alert message, a poison alert message, a credit return message, and acknowledgements.

US Patent:

20170123894, May 4, 2017

Filed:

Sep 14, 2016

Appl. No.:

15/264680

Inventors:

- Santa Clara CA, US
Robert G. Blankenship - Tacoma WA, US
Jeffrey C. Swanson - Sunnyvale CA, US
Robert J. Safranek - Portland OR, US

International Classification:

G06F 11/10
G06F 13/42
H03M 13/09

Abstract:

Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more of the slots. In another aspect, the flit is to include two or more slots, a payload, and a cyclic redundancy check (CRC) field to be encoded with a 16-bit CRC value generated based on the payload. The flit is sent over a serial data link to a device for processing, based at least in part on the three or more slots.