Jennifer L Hester

US Patent:

6879494, Apr 12, 2005

Filed:

May 27, 2003

Appl. No.:

10/447162

Inventors:

Longqiang L. Zu - Phoenix AZ, US
Jennifer A. Hester - Avondale AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K007/10
H05K007/12

US Classification:

361768, 361720, 361760, 257773, 257775, 174261, 174262

Abstract:

A circuit package has been described for routing long traces between an electronic circuit, such as a phase locked loop, and external circuit components. The traces are routed through two substrates. In each substrate, the traces are routed primarily on a layer adjacent to and between a pair ground planes located close to the traces. Degassing apertures are located to the side of the long traces to avoid interfering with the shielding provided by the grounds planes. The circuit package uses two power plated through holes and two ground plated through holes to reduce the noise on the power supply lines. The circuit package also separates the signal carrying plated through holes from the power plated through holes, which reduces noise on the long traces. Noise is further reduced on the long traces by using the ground plated through holes to shield the signal carrying plated through holes from noise generated at the power plated through holes.

US Patent:

20060138639, Jun 29, 2006

Filed:

Dec 28, 2004

Appl. No.:

11/024059

Inventors:

David Figueroa - Tolleson AZ, US
Jennifer Hester - Litchfield Park AZ, US
Yuan-Liang Li - Chandler AZ, US

International Classification:

H01L 23/12

US Classification:

257700000

Abstract:

According to some embodiments, an apparatus includes a first conductive pad, a first conductive plane, first dielectric material disposed between the first conductive plane and the first conductive pad, a second conductive plane, second dielectric material disposed between the first conductive plane and the second conductive plane, and a first conductive network. The first conductive network includes a first microvia within the first dielectric material and coupled to the first conductive pad, a first conductive trace within the first conductive plane and coupled to the first microvia, a second microvia within the second dielectric material and coupled to the first conductive trace, a second conductive trace within the second conductive plane and coupled to the second microvia, a third microvia within the second dielectric material and coupled to the second conductive trace, a third conductive trace within the first conductive plane and coupled to the third microvia, and a fourth microvia within the second dielectric material and coupled to the third conductive trace.

US Patent:

6594153, Jul 15, 2003

Filed:

Jun 27, 2000

Appl. No.:

09/605524

Inventors:

Longqiang L. Zu - Phoenix AZ
Jennifer A. Hester - Avondale AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K 111

US Classification:

361792, 361788, 361760, 361683, 361784, 174250, 174255

Abstract:

A circuit package has been described for routing long traces between an electronic circuit, such as a phase locked loop, and external circuit components. The traces are routed through two substrates. In each substrate, the traces are routed primarily on a layer adjacent to and between a pair ground planes located close to the traces. Degassing apertures are located to the side of the long traces to avoid interfering with the shielding provided by the grounds planes. The circuit package uses two power plated through holes and two ground plated through holes to reduce the noise on the power supply lines. The circuit package also separates the signal carrying plated through holes from the power plated through holes, which reduces noise on the long traces. Noise is further reduced on the long traces by using the ground plated through holes to shield the signal carrying plated through holes from noise generated at the power plated through holes.