Jennifer Wang

US Patent:

6918062, Jul 12, 2005

Filed:

Sep 28, 2001

Appl. No.:

09/968351

Inventors:

Jennifer C. Wang - Tempe AZ, US
Aniruddha P. Joshi - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F011/00

US Classification:

714 43, 714 4, 714 11

Abstract:

The present invention relates to a system and method to implement a cost-effective remote system management mechanism using a serial communication controller and interrupts. The system includes a requesting device operatively coupled to a network to send a status query through a serial port in the requesting device. The system further includes a responding device operatively coupled to the network to receive the status query from the requesting device. The status query inquires about operational status of the responding device. The responding device receives the status query through a serial port in the responding device, processes the status query, and reports the operational status through the serial port in the responding device to the requesting device in response to the status query sent by the requesting device.

US Patent:

6922741, Jul 26, 2005

Filed:

Feb 1, 2002

Appl. No.:

10/060336

Inventors:

Robert Burton - Gilbert AZ, US
Jennifer Wang - Tempe AZ, US
Aniruddha Joshi - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F013/28

US Classification:

710 28, 710 24, 710 25, 710 27

Abstract:

Embodiments of the invention provide a status register for each channel of a DMA controller. The status register may be used to monitor and record events that occur during DMA data transfers, including timeouts and aborts.

US Patent:

6944796, Sep 13, 2005

Filed:

Jun 27, 2002

Appl. No.:

10/180508

Inventors:

Aniruddha P. Joshi - Chandler AZ, US
Peter R. Munguia - Chandler AZ, US
Jennifer C. Wang - Tempe AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F011/00

US Classification:

714 43, 714 18

Abstract:

Embodiments of the present invention provide a system event log for a computer system. The system event log may comprise a RAM coupled to a system bus. The system event log may be configured to record information in the RAM corresponding to bus transactions on the system bus. The information may be used to de-bug system problems.

US Patent:

7111103, Sep 19, 2006

Filed:

Mar 22, 2002

Appl. No.:

10/104341

Inventors:

Jennifer C. Wang - Tempe AZ, US
Aniruddha P. Joshi - Chandler AZ, US
Peter R. Munguia - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/36
G06F 13/14

US Classification:

710306, 710305, 710310

Abstract:

A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of devices, and are accessible through the second bridge. A hub interface allows data to transfer downstream from the first bridge to the second bridge, and allows data to transfer upstream from the second bridge to the first bridge. A controller, external to the first and second bridges, accesses the configuration registers via the second bridge. A logic device allows the second bridge to send data to, and receive data from, the controller.

US Patent:

7346725, Mar 18, 2008

Filed:

Aug 3, 2006

Appl. No.:

11/462264

Inventors:

Jennifer C. Wang - Tempe AZ, US
Aniruddha P. Joshi - Chandler AZ, US
Peter R. Munguia - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710306, 710309, 710313

Abstract:

A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of devices, and are accessible through the second bridge. A hub interface allows data to transfer downstream from the first bridge to the second bridge, and allows data to transfer upstream from the second bridge to the first bridge. A controller, external to the first and second bridges, accesses the configuration registers via the second bridge. A logic device allows the second bridge to send data to, and receive data from, the controller.

US Patent:

8539131, Sep 17, 2013

Filed:

Sep 23, 2010

Appl. No.:

12/888807

Inventors:

Jennifer C. Wang - Tempe AZ, US
Alejandro Lenero Beracoechea - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/14

US Classification:

710305, 710306, 710240

Abstract:

Systems and methods of operating root hub host controllers provide for determining, at a protocol engine having a dedicated port, a speed of a device in response to a coupling of the device to the dedicated port. Data transfer can occur at a second speed between software interface logic of the host controller and the protocol engine, and at the first speed between the protocol engine and the device via the dedicated port, wherein the second speed is greater than the first speed. In addition, data may be transferred in unicast transactions in which no split tokens are exchanged.

US Patent:

8626979, Jan 7, 2014

Filed:

Dec 22, 2010

Appl. No.:

12/975613

Inventors:

Jennifer C. Wang - Tempe AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/36

US Classification:

710315, 709230

Abstract:

A signal transmission system includes a controller interface, a protocol engine to convert data based on at least one protocol, and a common protocol interface coupled between the controller interface and the protocol engine. The controller interface includes or is coupled to a common dispatcher, and the data is to be transmitted between the controller interface and protocol engine through the common protocol interface and common dispatcher. The same protocol engine may convert data into different protocols, with all of the converted data be transmitted to or received from the controller interface through the common dispatcher and common protocol interface.

US Patent:

20030212844, Nov 13, 2003

Filed:

May 10, 2002

Appl. No.:

10/143165

Inventors:

Jennifer Wang - Tempe AZ, US
Aniruddha Joshi - Chandler AZ, US

International Classification:

G06F013/24
G06F013/32

US Classification:

710/266000

Abstract:

According to one embodiment of the invention, a first signal line is provided for a serial interface unit (SIU) of an I/O controller to report interrupt requests to an interrupt controller. In one embodiment, a transition of the first signal line from a first level (e.g., low level or logic 0) to a second level (e.g., high level or logic 1) indicates a pending interrupt to the interrupt controller. A pull up resistor is provided to pull the first signal line to the second level when the first signal line is not driven by the SIU. In response to detecting an interrupt request initiated by an I/O device, a transition from the first level to the second level is generated on the first signal line for a predetermined duration to report the pending interrupt request to the interrupt controller.