Jennifer Chen Wong

US Patent:

6353341, Mar 5, 2002

Filed:

Nov 12, 1999

Appl. No.:

09/439844

Inventors:

Austin H. Lesea - Los Gatos CA
Peter H. Alfke - Los Altos Hills CA
Jennifer Wong - Fremont CA
Steven P. Young - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G01R 2902

US Classification:

327 34, 327205

Abstract:

A clock signal is monitored to detect a transition from a first logic state to a second logic state. Once this transition is detected, subsequent transitions of the clock signal are ignored for a predetermined time period during which signal interference is most significant. After lapse of the predetermined time period, the clock signal is again monitored to detect subsequent state transitions. In some embodiments, the clock signal is delayed using a delay circuit to produce a delayed clock signal which is used to force the clock signal to the second logic state for a predetermined time period. In one embodiment, the predetermined time period is user-selectable via one or more selectable taps on the delay circuit.

US Patent:

6366117, Apr 2, 2002

Filed:

Nov 28, 2000

Appl. No.:

09/724973

Inventors:

Raymond C. Pang - San Jose CA
Jennifer Wong - Fremont CA
Scott O. Frake - Cupertino CA
Jane W. Sowards - Fremont CA
Venu M. Kondapalli - Sunnyvale CA
F. Erich Goetting - Cupertino CA
Stephen M. Trimberger - San Jose CA
Kameswara K. Rao - San Jose CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04L 900

US Classification:

326 38, 380 44, 713189, 326 40

Abstract:

It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, the encrypted design is decrypted by a key or keys within the PLD that are preserved when power is removed by either being stored in nonvolatile memory or by being backed up with a battery that switches into operation when the power is removed from the PLD.

US Patent:

6441641, Aug 27, 2002

Filed:

Nov 28, 2000

Appl. No.:

09/724735

Inventors:

Raymond C. Pang - San Jose CA
Venu M. Kondapalli - Sunnyvale CA
Jane W. Sowards - Fremont CA
Scott O. Frake - Cupertino CA
Jennifer Wong - Fremont CA
F. Erich Goetting - Cupertino CA
Peter H. Alfke - Los Altos Hills CA
Schuyler E. Shimanek - Albuquerque NM

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H01L 2500

US Classification:

326 41, 326 37, 326 46

Abstract:

A PLD can be manufactured to include power supply lines from two sources so that a portion of the PLD can be backed up with a battery when power to the PLD is removed. A switch that supplies power to the backed up portion of the PLD receives power from both an external power supply and from the battery, and detects voltage level of the external power supply, switching to battery power when voltage from the external power supply is not sufficient.

US Patent:

6480954, Nov 12, 2002

Filed:

Jun 6, 2001

Appl. No.:

09/876745

Inventors:

Stephen M. Trimberger - San Jose CA
Richard A. Carberry - Los Gatos CA
Robert Anders Johnson - San Jose CA
Jennifer Wong - Fremont CA

Assignee:

Xilinx Inc. - San Jose CA

International Classification:

G06F 900

US Classification:

713 1, 713100, 713501, 713600

Abstract:

A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data.

US Patent:

6803786, Oct 12, 2004

Filed:

Mar 11, 2003

Appl. No.:

10/386955

Inventors:

Goran Bilski - San Jose CA
Ralph D. Wittig - Menlo Park CA
Jennifer Wong - Fremont CA
David B. Squires - Palo Alto CA

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 38, 326 39

Abstract:

Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.

US Patent:

6931543, Aug 16, 2005

Filed:

Nov 28, 2000

Appl. No.:

09/724652

Inventors:

Raymond C. Pang - San Jose CA, US
Walter N. Sze - Saratoga CA, US
Jennifer Wong - Fremont CA, US
Stephen M. Trimberger - San Jose CA, US
John M. Thendean - Berkely CA, US
Kameswara K. Rao - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F017/00

US Classification:

713193, 713 1, 713100

Abstract:

To prevent copying of a design implemented in a programmable logic device (PLD), the PLD itself stores a decryption key or keys loaded by the designer, and includes a decryptor for decrypting an encrypted configuration bitstream as it is loaded into the PLD. The PLD also includes logic for reading header information that indicates whether the bitstream is encrypted, and can accept both encrypted and unencrypted bitstreams. The encryption keys may be stored in non-volatile memory or backed up with a battery so that they are retained when power is removed.

US Patent:

6946874, Sep 20, 2005

Filed:

Aug 27, 2004

Appl. No.:

10/927750

Inventors:

Goran Bilski - Molndal, SE
Ralph D. Wittig - Menlo Park CA, US
Jennifer Wong - Fremont CA, US
David B. Squires - Palo Alto CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K019/0177

US Classification:

326 41, 326 38, 326 39

Abstract:

Structures and methods of including processor capabilities in an existing PLD architecture with minimal disruption to the existing general interconnect structure. In a PLD including a column of block RAM (BRAM) blocks, the BRAM blocks are modified to create specialized logic blocks including a RAM, a processor, and a dedicated interface coupled between the RAM, the processor, and the general interconnect structure of the PLD. The additional area is obtained by increasing the width of the column of BRAM blocks. Because the interconnect structure remains virtually unchanged, the interconnections between the specialized logic blocks and the adjacent tiles are already in place, and the modifications do not affect the PLD routing software. In some embodiments, the processor can be optionally disabled, becoming transparent to the user. Other embodiments provide methods of modifying a PLD to include the structures and provide the capabilities described above.

US Patent:

6957340, Oct 18, 2005

Filed:

Nov 28, 2000

Appl. No.:

09/724873

Inventors:

Raymond C. Pang - San Jose CA, US
Stephen M. Trimberger - San Jose CA, US
Jennifer Wong - Fremont CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H04L009/14

US Classification:

713189, 326 38, 326 39

Abstract:

It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted bitstream could be observed and copied as it is being loaded. According to the invention, a bitstream for configuring a PLD with an encrypted design includes unencrypted words for controlling loading of the configuration bitstream and encrypted words that actually specify the design.