Jerald Keith Alston from Coto de Caza, CA, age 68

Resumes

Jerald Alston

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Us Patents

Method And System For Using An In-Line Credit Extender With A Host Bus Adapter
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US Patent:

7380030, May 27, 2008
Filed:

Oct 1, 2004
Appl. No.:

10/956718
Inventors:

Oscar J. Grijalva - Cypress CA, US
Jerald K. Alston - Coto de Caza CA, US
Eric R. Griffith - Yorba Linda CA, US
James A. Kunz - Plymouth MN, US
Assignee:

QLOGIC, Corp. - Aliso Viejo CA
International Classification:

G06F 3/00
US Classification:

710 57, 710 52, 709220, 709221, 709222
Abstract:

A storage area network (“SAN”) and a system is provided. The SAN includes, a host bus adapter operationally coupled with a credit extender, wherein the credit extender receives frames from a Fibre Channel network and sends the received frames to the HBA based on buffer space available in the HBA. The HBA notifies other Fibre Channel ports of buffer space available in the credit extender. The HBA sends a signal to the credit extender notifying the credit extender of available buffer space in the HBA. The HBA includes a management port for interfacing the HBA with the credit extender.

Method And System For Dma Optimization
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US Patent:

7577773, Aug 18, 2009
Filed:

Sep 9, 2005
Appl. No.:

11/222936
Inventors:

Rajendra R. Gandhi - Laguna Niguel CA, US
Kuangfu D. Chu - Irvine CA, US
Jerald K. Alston - Coto de Caza CA, US
Assignee:

QLOGIC, Corporation - Aliso Viejo CA
International Classification:

G06F 13/28
US Classification:

710 22, 718101
Abstract:

Method and system for processing read requests sent by a network interface device to a host system is provided. The method includes sending staggered read requests within a programmable time interval (“T”), wherein a transmit direct memory access (DMA) module sends more than one read request to the host system within the time interval T; placing data received from the host system in response to the read requests in independent slots of a transmit buffer; and unloading the transmit buffer slots based on an unload command, wherein the unload command is based on a mapping of read requests corresponding to transmit buffer slot locations where data from the host system is stored, and data is sent from the transmit buffer to a network device in the same order as the read requests that are sent from the network interface device to host system.

Method And System For Quality Of Service In Host Bus Adapters
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US Patent:

7668177, Feb 23, 2010
Filed:

Jan 31, 2007
Appl. No.:

11/669573
Inventors:

Darren L. Trapp - Orange CA, US
Sanjaya Anand - Coto De Caza CA, US
Jerald K. Alston - Coto De Caza CA, US
Assignee:

QLOGIC, Corporation - Aliso Viejo CA
International Classification:

H04L 12/28
US Classification:

37039542, 370412
Abstract:

Method and system for an adapter coupled to a network via a network link is provided. The method includes using a first selectable mode and a second selectable mode to provide quality of service to a plurality of applications executed by one or more computing system. In the first selectable mode, the quality of service is based on allocating bandwidth of the network link and dynamically adjusting an initial priority assigned to a plurality of queues, each queue being associated with an application from among a plurality of applications. In the second selectable mode, the quality of service is based on a user assigning a priority to each of the plurality of applications and the adapter determines a number of input/output (I/O) requests it needs to process within a duration and then transfers information based on the determined number of I/O requests and the assigned priority.

Method And System For Storing Frames In Networks
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US Patent:

7668978, Feb 23, 2010
Filed:

Feb 17, 2006
Appl. No.:

11/357515
Inventors:

David T Kwak - Newport Coast CA, US
Ali A. Khwaja - Irvine CA, US
Jerald K. Alston - Coto de Caza CA, US
Assignee:

QLOGIC, Corporation - Aliso Viejo CA
International Classification:

G06F 3/00
G06F 15/167
G06F 13/00
US Classification:

710 14, 710 8, 709215, 711147
Abstract:

Method and system for an adapter operationally coupled to a host system and a network is provided. The adapter includes an internal memory that can be configured in a first mode to operate as a dedicated random access memory used by a main processor of the adapter; or configured in a second mode to operate both as a random access memory used by the main processor and also used for storing information received from the network. The method includes enabling the second mode of the internal memory so that the internal memory is configured to operate both as random access memory for the main processor and for storing information received from the network.

Method And System For Sharing Input/Output Devices
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US Patent:

7694047, Apr 6, 2010
Filed:

Feb 16, 2006
Appl. No.:

11/355622
Inventors:

Jerald K. Alston - Coto de Caza CA, US
Assignee:

QLOGIC, Corporation - Aliso Viejo CA
International Classification:

G06F 13/38
US Classification:

710 62, 710 38
Abstract:

A PCI-Express module that is coupled to plural host systems and to at least an input/output (I/O) device is provided. The PCI-Express module includes an upstream port module and a downstream port module that use a mapping table to facilitate the plural host systems sharing the I/O device by modifying a transaction layer packet (TLP) field. For upstream ID based traffic, a source identifier is replaced based on the mapping table and a destination identifier is replaced with a value that is captured during upstream port module initialization. For upstream address based traffic, the mapping table routes TLPs by using a downstream port number and a function number in a source identification field. For downstream ID based traffic, a destination identifier is replaced by using the mapping table for routing TLPs. For downstream address based traffic, the PCI-Express module uses an address map to route TLPs.

Method And System For Optimizing Data Transfer In Networks
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US Patent:

20060064531, Mar 23, 2006
Filed:

Sep 23, 2004
Appl. No.:

10/948404
Inventors:

Jerald Alston - Coto de Caza CA, US
Oscar Grijalva - Cypress CA, US
International Classification:

G06F 13/36
US Classification:

710308000
Abstract:

A method and system for transferring data from a host system to plural devices is provided. Each device may be coupled to a link having a different serial rate for accepting data from the host system. The system includes plural programmable DMA channels, which are programmed to concurrently transmit data at a rate at which the receiving devices will accept data. The method includes programming a DMA channel that can transmit data at a rate similar to the rate at which the receiving device will accept data.

Add-On Card With Automatic Bus Power Line Selection Circuit
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US Patent:

63276356, Dec 4, 2001
Filed:

Mar 30, 1999
Appl. No.:

9/281369
Inventors:

Jerald K. Alston - Portola Hills CA
Mark L. Craven - Laguna Hills CA
Henry Tran - Irvine CA
Assignee:

QLogic Corporation - Aliso Viejo CA
International Classification:

G06F 1300
US Classification:

710101
Abstract:

An add-on card is provided for use within a computer system that has an expansion slot connected to a bus. The bus has a first supply line for supplying a first predetermined voltage and a second supply line for supplying a second predetermined voltage which is higher than the first predetermined voltage. The add-on card is adapted to operate properly regardless of whether the respective predetermined voltages are supplied on (1) the first supply line only, (2) the second supply line only, or (3) both supply lines. In a PCI bus implementation, where 3. 3V and 5V are the predetermined voltage levels, the add-on card operates properly regardless of whether: only a 5V level is provided, only a 3. 3V level is provided, or both 3. 3V and 5V levels are provided.

Synchronization Circuit For Transferring Pointer Between Two Asynchronous Circuits
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US Patent:

60552859, Apr 25, 2000
Filed:

Nov 17, 1997
Appl. No.:

8/971387
Inventors:

Jerald Alston - Portola Hills CA
Assignee:

QLogic Corporation - Aliso Viejo CA
International Classification:

H04L 2540
US Classification:

375372
Abstract:

A synchronization circuit synchronizes the transfer of pointer values from a transmitting circuit operating in a first clock domain to a receiving circuit operating in a second clock domain, wherein the first clock domain and the second clock domain are mutually asynchronous. An input latch operating in response to a first synchronization signal generated in the first clock domain transfers a pointer value to a latched pointer bus. The first synchronization signal is provided as an input to a synchronization section which generates a second synchronization signal in the second clock domain. The second synchronization signal enables an output latch to transfer the pointer value on the latched pointer bus to an output bus. The pointer value on the output bus is thus synchronized in the second clock domain. The second synchronization signal is then provided as an input to a synchronization section which generates the first synchronization signal in the first clock domain.