Jeremiah S Mccarthy

US Patent:

44160550, Nov 22, 1983

Filed:

Dec 4, 1981

Appl. No.:

6/327383

Inventors:

Jeremiah P. McCarthy - Framingham MA
Marvin Tabasky - Peabody MA

Assignee:

GTE Laboratories Incorporated - Waltham MA

International Classification:

H01L 2131
H01L 21318

US Classification:

29577C

Abstract:

Method of fabricating monolithic integrated circuit structure incorporating a bipolar transistor and a high value resistor. First and second N-type sectors are formed in an N-type epitaxial layer by junction isolation. A silicon oxide layer is formed on the surface of the body. The layer is thinner over a part of the first sector and over a part of the second sector. A layer of silicon nitride is formed on portions of the thinner silicon oxide to overlie predetermined zones within each sector. P-type conductivity imparting material is ion implanted through the unprotected thinner silicon oxide to form a low resistivity region in the first sector and two low resistivity regions in the second sector. The layer of silicon nitride overlying the predetermined zone in the second sector is removed, and an opening is formed over the predetermined zone in the second sector. P-type conductivity imparting material is ion implanted through the opening to form a resistor in the predetermined zone of the second sector with the two low resistivity regions providing contact regions at opposite ends thereof.