Jeremiah Mccarthy

US Patent:

44634919, Aug 7, 1984

Filed:

Apr 23, 1982

Appl. No.:

6/371325

Inventors:

Ernest A. Goldman - Stow MA
Jeremiah P. McCarthy - Framingham MA
Paul E. Poppert - Acton MA

Assignee:

GTE Laboratories Incorporated - Waltham MA

International Classification:

H01L 2182
H01L 2188
H01L 21225

US Classification:

29571

Abstract:

Method of fabricating a monolithic integrated circuit structure incorporating complementary metal-oxide-silicon field effect transistors (CMOS FET's) including providing a body of silicon produced by conventional techniques having a sector of N-type and a sector of P-type each covered by a thin silicon oxide layer and a thin silicon nitride layer. The regions of the body adjacent to each of the sectors are covered by a thicker silicon oxide field layer. Portions of the thin nitride and oxide layers are removed to expose spaced apart zones in each of the sectors. Adherent contact members of low resistivity polycrystalline silicon of N and P-type conductivity are formed in contact with the exposed surfaces of the zone in the P and N-type sectors, respectively. Where N and P-type contact members are contiguous a rectifying junction is produced. The surfaces of the polycrystalline contact members are metallized with a highly conductive material, thereby shorting out the rectifying junctions.

US Patent:

44160550, Nov 22, 1983

Filed:

Dec 4, 1981

Appl. No.:

6/327383

Inventors:

Jeremiah P. McCarthy - Framingham MA
Marvin Tabasky - Peabody MA

Assignee:

GTE Laboratories Incorporated - Waltham MA

International Classification:

H01L 2131
H01L 21318

US Classification:

29577C

Abstract:

Method of fabricating monolithic integrated circuit structure incorporating a bipolar transistor and a high value resistor. First and second N-type sectors are formed in an N-type epitaxial layer by junction isolation. A silicon oxide layer is formed on the surface of the body. The layer is thinner over a part of the first sector and over a part of the second sector. A layer of silicon nitride is formed on portions of the thinner silicon oxide to overlie predetermined zones within each sector. P-type conductivity imparting material is ion implanted through the unprotected thinner silicon oxide to form a low resistivity region in the first sector and two low resistivity regions in the second sector. The layer of silicon nitride overlying the predetermined zone in the second sector is removed, and an opening is formed over the predetermined zone in the second sector. P-type conductivity imparting material is ion implanted through the opening to form a resistor in the predetermined zone of the second sector with the two low resistivity regions providing contact regions at opposite ends thereof.

US Patent:

42814480, Aug 4, 1981

Filed:

Apr 14, 1980

Appl. No.:

6/140036

Inventors:

Vincent J. Barry - Hudson MA
Jeremiah P. McCarthy - Framingham MA

Assignee:

GTE Laboratories Incorporated - Waltham MA

International Classification:

H01L 2176
H01L 2710
H01L 2956

US Classification:

29577C

Abstract:

Method of fabricating monolithic integrated circuit structure incorporating a full-wave diode bridge rectifier of four Schottky diodes. A body of silicon is produced by growing an epitaxial layer of N-type silicon on a P-type substrate. P-type imparting material is diffused into the layer to form isolating barriers delineating first and second N-type zones separated from each other by intervening P-type material and third and fourth N-type zones which are contiguous. A mixture of titanium and tungsten is deposited on portions of the zones and heated to form a mixed silicide. Schottky rectifying barriers are produced at the interfaces of the mixed silicide and N-type zones. Conductive members are formed; a first conductive member is connected to the N-type material of the first zone and the silicide of the third zone, a second conductive member is connected to the N-type material of the second zone and the silicide of the fourth zone, a third conductive member is connected in common to the silicide of the first and second zones, and a fourth conductive member is connected to the N-type material of the third and fourth zones. An AC voltage applied across the first and second conductive members produces a DC voltage across the third and fourth conductive members.

US Patent:

44982232, Feb 12, 1985

Filed:

Apr 23, 1982

Appl. No.:

6/371326

Inventors:

Ernest A. Goldman - Stow MA
Jeremiah P. McCarthy - Framingham MA
Paul E. Poppert - Acton MA

Assignee:

GTE Laboratories Incorporated - Waltham MA

International Classification:

H01L 21265

US Classification:

29571

Abstract:

A body of silicon has sectors of N-type and P-type covered by silicon oxide gate layers with adjacent regions covered by a thicker silicon oxide field layer. Gate members of N-type polycrystalline silicon are placed on the gate layers to define an N-type channel region in the N-type sector and a P-type channel region is the P-type sector. P-type conductivity imparting material is introduced into the remaining regions of the N-type sector to convert them to P-type source/drain regions with an intervening N-type channel region, and N-type conductivity imparting material is introduced into the remaining regions of the P-type sector to convert them to N-type source/drain regions with an intervening P-type channel region. The exposed silicon oxide is grown to a thicker field layer and a protective oxide is formed on the polycrystalline gate members. The source/drain regions are exposed and adherent contact members of polycrystalline silicon of N and P-type are formed in ohmic contact with the source/drain regions of N and P-type, respectively.