NVIDIA since Jan 2008
Physical Design Engineer
Sun Microsystems Feb 2005 - Jan 2007
Physical Design Engineer
Credence Feb 2003 - Feb 2005
ASIC Engineer
Azanda Network Devices Jan 2001 - Jan 2003
MTS
Avanti Corp 1998 - 2000
Library AE
Education:
Santa Clara University 2006 - 2009
MS, Electrical Engineer
State University of New York at Binghamton 1993 - 1997
BS
Skills:
Cadence Virtuoso System on A Chip Floorplanning Very Large Scale Integration Integrated Circuits Perl Rtl Design Ic Arm Processors Asic Timing Vlsi Verilog Arm Architecture Tcl Soc Eda Primetime Timing Closure Semiconductors Design Physical Design Static Timing Analysis Route Low Power Design Application Specific Integrated Circuits Routing