Jerome Heath Johnson

US Patent:

6356972, Mar 12, 2002

Filed:

Jan 19, 2001

Appl. No.:

09/765773

Inventors:

Kenneth T. Chin - Cypress TX
Clarence K. Coffee - Pembroke Pines FL
Michael J. Collins - Tomball TX
Jerome J. Johnson - Spring TX
Phillip M. Jones - Spring TX
Robert A. Lester - Houston TX
Gary J. Piccirillo - Cypress TX

Assignee:

Compaq Information Technologies Group, LP - Houston TX

International Classification:

G06F 1314

US Classification:

710310

Abstract:

A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues. Data ensuing from the request can be re-ordered and presented to the destination based on the current pointer position within the in-order queue.

US Patent:

6505260, Jan 7, 2003

Filed:

Feb 15, 2001

Appl. No.:

09/784690

Inventors:

Kenneth T. Chin - Cypress TX
C. Kevin Coffee - Pembroke Pines FL
Michael J. Collins - Pleasonton CA
Jerome J. Johnson - Spring TX
Phillip M. Jones - Spring TX
Robert A. Lester - Houston TX
Gary J. Piccirillo - Cypress TX
Jeffrey C. Stevens - Spring TX

Assignee:

Compaq Information Technologies Group, L.P. - Houston TX

International Classification:

G06F 1318

US Classification:

710 41, 710 42, 711151

Abstract:

A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming âmemory-starved. â Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.

US Patent:

6640282, Oct 28, 2003

Filed:

Jan 25, 2001

Appl. No.:

09/769716

Inventors:

John M. MacLaren - Cypress TX
Jerome J. Johnson - Spring TX
Robert A. Lester - Tomball TX
Gary J. Piccirillo - Cypress TX
John E. Larson - Houston TX
Christian H. Post - Spring TX
Jeffery Galloway - The Woodlands TX
Ho M. Lai - Spring TX
Eric Rose - Austin TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1216

US Classification:

711115, 711157, 710302, 365 52, 365 63, 365226

Abstract:

The control logic for a hot-pluggable memory cartridge for use in a redundant memory system. To implement a hot-pluggable memory cartridge in a redundant memory system, control logic to control the sequence of events for powering-up and powering-down a memory cartridge is provided.

US Patent:

6684292, Jan 27, 2004

Filed:

Sep 28, 2001

Appl. No.:

09/966892

Inventors:

Gary J. Piccirillo - Cypress TX
Jerome J. Johnson - Spring TX
John E. Larson - Houston TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1200

US Classification:

711106, 711162, 36518525, 714 7, 710302

Abstract:

A technique for resynchronizing a memory system. More specifically, a technique for resynchronizing a plurality of memory segments in a redundant memory system after a hot-plug event. After a memory cartridge is hot-plugged into a system, the memory cartridge is synchronized with the operational memory cartridges such that the memory system can operate in lock step. A refresh counter in each memory cartridge is disabled to generate a first refresh request to the corresponding memory segments in the memory cartridge. After waiting a period of time to insure that regardless of what state each memory cartridge is in when the first refresh request is initiated all cycles have been completely executed, each refresh counter is re-enabled, thereby generating a second refresh request. The generation of the second refresh request to each of the memory segments provides synchronous operation of each of the memory cartridges.

US Patent:

6766469, Jul 20, 2004

Filed:

Jan 25, 2001

Appl. No.:

09/769783

Inventors:

John E. Larson - Houston TX
John M. MacLaren - Cypress TX
Jerome J. Johnson - Spring TX
Gary J. Piccirillo - Cypress TX
Robert A. Lester - Tomball TX
Christian H. Post - Spring TX
Jeffery Galloway - The Woodlands TX
Anisha Anand - Houston TX
Ho M. Lai - Spring TX
Eric Rose - Austin TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1100

US Classification:

714 7, 714 5, 711115, 710302

Abstract:

A method of replacing a memory module in a computer system. Specifically, a method for replacing a memory module in a segment of a redundant memory system, without powering-down the memory system.

US Patent:

6785785, Aug 31, 2004

Filed:

Jan 25, 2001

Appl. No.:

09/770759

Inventors:

Gary J. Piccirillo - Cypress TX
John M. MacLaren - Cypress TX
Robert A. Lester - Tomball TX
John E. Larson - Houston TX
Jerome J. Johnson - Spring TX
Benjamin H. Clark - Spring TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1200

US Classification:

711157, 711114, 714710, 714763

Abstract:

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules.

US Patent:

6785835, Aug 31, 2004

Filed:

Jan 25, 2001

Appl. No.:

09/769957

Inventors:

John M. MacLaren - Cypress TX
Paul Santeler - Cypress TX
Kenneth A. Jansen - Spring TX
Sompong P. Olarig - Pleasanton CA
Robert A. Lester - Tomball TX
Patrick L. Ferguson - Cypress TX
John E. Larson - Houston TX
Jerome J. Johnson - Spring TX
Gary J. Piccirillo - Cypress TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1100

US Classification:

714 6, 714764, 714770, 711114

Abstract:

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The system supports DIMMs having X4 and X8 configurations. The system also transitions between various states, including a redundant state and a non-redundant state, to facilitate âhot-plugâ capabilities utilizing its removable memory cartridges.

US Patent:

6832286, Dec 14, 2004

Filed:

Jun 25, 2002

Appl. No.:

10/179081

Inventors:

Jerome J. Johnson - Spring TX
Benjamin H. Clark - Spring TX
Gary J. Piccirillo - Cypress TX
John M. MacLaren - Cypress TX

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1200

US Classification:

711105, 711167

Abstract:

A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). To optimally run back to back cycles to the memory modules, a technique for providing de-rating parameters such that unnecessary latencies designed into the memory devices can be removed while the system is executing requests. By removing any unnecessary latency, cycle time and overall system performance can be improved.