Jerry Edward Gray

US Patent:

43297030, May 11, 1982

Filed:

Apr 18, 1980

Appl. No.:

6/141321

Inventors:

Ury Priel - Cupertino CA
Jerry D. Gray - San Jose CA
Allen H. Frederick - Pacifica CA

Assignee:

Monolithic Memories, Inc. - Sunnyvale CA

International Classification:

H01L 2972
H01L 2978
H01L 2702
H01L 2704

US Classification:

357 35

Abstract:

Shallow, boron implanted regions are formed by ion implanting. Disclosed is a PNP transistor device (lateral type) having a P type emitter region preferably made with a boron implant.

US Patent:

41526279, May 1, 1979

Filed:

Jun 10, 1977

Appl. No.:

5/805534

Inventors:

Ury Priel - Cupertino CA
Jerry D. Gray - San Jose CA
Allen H. Frederick - Pacifica CA

Assignee:

Monolithic Memories Inc. - Sunnyvale CA

International Classification:

G11C 1700
G11C 700

US Classification:

315227

Abstract:

This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense amplifier of the memory array are fabricated to have a high resistivity thereby permitting the semiconductor array to operate with much lower power. The high resistivity semiconductor resistors of this write-once, read-only semiconductor memory array are fabricated using an ion implantation step, preferably, between the base and emitter diffusion process steps in fabricating the NPN transistor structures used in the bit line and word line decoders or the memory array. The high resistivity ion implanted resistor regions are preferably shallow, boron implanted regions that are formed by ion implanting through a thin silicon dioxide layer. Various resistor devices are disclosed using shallow, boron implanted, high resistivity regions.

US Patent:

41962281, Apr 1, 1980

Filed:

Jul 21, 1978

Appl. No.:

5/926626

Inventors:

Ury Priel - Cupertino CA
Jerry D. Gray - San Jose CA
Allen H. Frederick - Pacifica CA

Assignee:

Monolithic Memories, Inc. - Sunnyvale CA

International Classification:

H01L 21425
H01L 21441

US Classification:

427 88

Abstract:

This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense amplifier of the memory array are fabricated to have a high resistivity thereby permitting the semiconductor array to operate with much lower power. The high resistivity semiconductor resistors of this write-once, read-only semiconductor memory array are fabricated using an ion implantation step, preferably, between the base and emitter diffusion process steps in fabricating the NPN transistor structures used in the bit line and word line decoders of the memory array. The high resistivity ion implanted resistor regions are preferably shallow, boron implanted regions that are formed by ion implanting through a thin silicon dioxide layer. Various resistor devices are disclosed using shallow, boron implanted, high resistivity regions.

US Patent:

42284511, Oct 14, 1980

Filed:

Jul 21, 1978

Appl. No.:

5/926856

Inventors:

Ury Priel - Cupertino CA
Jerry D. Gray - San Jose CA
Allen H. Frederick - Pacifica CA

Assignee:

Monolithic Memories, Inc. - Sunnyvale CA

International Classification:

H01L 2702
H01L 2978
H01L 2972
H01C 1012

US Classification:

357 51

Abstract:

This disclosure relates to a low power write-once, read-only semiconductor memory (PROM or programmable read only memory) array wherein the semiconductor resistors located in the word line decoder and driver and also in the bit line decoder and sense amplifier of the memory array are fabricated to have a high resistivity thereby permitting the semiconductor array to operate with much lower power. The high resistivity semiconductor resistors of this write-once, read-only semiconductor memory array are fabricated using an ion implantation step, preferably, between the base and emitter diffusion process steps in fabricating the NPN transistor structures used in the bit line and word line decoders of the memory array. The high resistivity ion implanted resistor regions are preferably shallow, boron implanted regions that are formed by ion implanting through a thin silicon dioxide layer. Various resistor devices are disclosed using shallow, boron implanted, high resistivity regions.