Jerry P Pirog

US Patent:

20110225372, Sep 15, 2011

Filed:

Dec 22, 2010

Appl. No.:

12/976228

Inventors:

Jerry Pirog - Easton PA, US

International Classification:

G06F 12/08

US Classification:

711141, 711E12026

Abstract:

Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A state engine operates on instructions received from the multi-thread instruction engine, the instruction including a cache access request to a local cache of the state engine. A cache line entry manager of the state engine translates between a logical index value of data corresponding to the cache access request and a physical address of data stored in the local cache. The cache line entry manager manages data coherency of the local cache and allows one or more concurrent cache access requests to a given cache data line for non-overlapping data units.

US Patent:

20110225589, Sep 15, 2011

Filed:

Mar 12, 2011

Appl. No.:

13/046726

Inventors:

Jerry Pirog - Easton PA, US
Deepak Mital - Orefield PA, US
William Burroughs - Macungie PA, US

Assignee:

LSI CORPORATION - Milpitas CA

International Classification:

G06F 9/46
G06F 13/14

US Classification:

718102, 710305

Abstract:

Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A function bus interface inspects instructions received from the multi-thread instruction engine for one or more exception conditions. If the function bus interface detects an exception, the function bus interface reports the exception to the scheduler and the multi-thread instruction engine. The scheduler reschedules the thread corresponding to the instruction having the exception for processing in the multi-thread instruction engine. Otherwise, the function bus interface provides the instruction to a corresponding destination processing module of the network processor.

US Patent:

20110289179, Nov 24, 2011

Filed:

Jul 27, 2011

Appl. No.:

13/192140

Inventors:

Hakan I. Pekcan - Basking Ridge NJ, US
Steven J. Pollock - Allentown PA, US
Jerry Pirog - Easton PA, US

International Classification:

G06F 15/167

US Classification:

709213

Abstract:

Described embodiments provide a method of updating configuration data of a network processor having one or more processing modules and a shared memory. A control processor of the network processor writes updated configuration data to the shared memory and sends a configuration update request to a configuration manager. The configuration update request corresponds to the updated configuration data. The configuration manager determines whether the configuration update request corresponds to settings of a given one of the processing modules. If the configuration update request corresponds to settings of a given one of the one or more processing modules, the configuration manager, sends one or more configuration operations to a destination one of the processing modules corresponding to the configuration update request and updated configuration data. The destination processing module updates one or more register values corresponding to configuration settings of the processing module with the corresponding updated configuration data.

US Patent:

20130089098, Apr 11, 2013

Filed:

Nov 28, 2012

Appl. No.:

13/687911

Inventors:

LSI Corporation - Milpitas CA, US
James Clee - Orefield PA, US
Jerry Pirog - Easton PA, US
Te Khac Ma - Allentown PA, US
Steven J. Pollock - Allentown PA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H04L 29/06

US Classification:

370394

Abstract:

Described embodiments classify packets received by a network processor. A processing module of the network processor generates tasks corresponding to each received packet. A packet classification processor determines, independent of a flow identifier of the received task, control data corresponding to each task. A multi-thread instruction engine processes threads of instructions corresponding to received tasks, each task corresponding to a packet flow of the network processor and maintains a thread status table and a sequence counter for each flow. Active threads are tracked by the thread status table, and each status entry includes a sequence value and a flow value identifying the flow. Each sequence counter generates a sequence value for each thread by incrementing the sequence counter each time processing of a thread for the associated flow is started, and decrementing the sequence counter each time a thread for the associated flow is completed.

US Patent:

20130089109, Apr 11, 2013

Filed:

Nov 28, 2012

Appl. No.:

13/687719

Inventors:

LSI Corporation - Milpitas CA, US
James Clee - Orefield PA, US
Jerry Pirog - Easton PA, US

Assignee:

LSI CORPORATION - Milpitas CA

International Classification:

H04L 29/06

US Classification:

370431

Abstract:

Described embodiments provide a packet classifier for a network processor that generates tasks corresponding to each received packet. The packet classifier includes a scheduler to generate contexts corresponding to tasks received by the packet classifier from processing modules of the network processor. The packet classifier processes threads of instructions, each thread of instructions corresponding to a context received from the scheduler, and each thread associated with a data flow. A thread status table has N entries to track up to N active threads. Each status entry includes a valid status indicator, a sequence value, a thread indicator and a flow indicator. A sequence counter generates a sequence value for each data flow of each thread and is incremented when processing of a thread is started, and is decremented when a thread is completed. Instructions are processed in the order in which the threads were started for each data flow.

US Patent:

20200042479, Feb 6, 2020

Filed:

Oct 14, 2019

Appl. No.:

16/601137

Inventors:

- Santa Clara CA, US
Yipeng Wang - Hillsboro OR, US
Andrew Herdrich - Hillsboro OR, US
Tsung-Yuan C. Tai - Portland OR, US
Niall D. McDonnell - Limerick, IE
Hugh Wilkinson - Newton MA, US
Bradley A. Burres - Waltham MA, US
Bruce Richardson - Shannon, Claire, IE
Namakkal N. Venkatesan - Hillsboro OR, US
Debra Bernstein - Sudbury MA, US
Edwin Verplanke - Chandler AZ, US
Stephen R. Van Doren - Portland OR, US
An Yan - Orefield PA, US
Andrew Cunningham - Ennis, IE
David Sonnier - Austin TX, US
Gage Eads - Austin TX, US
James T. Clee - Orefield PA, US
Jamison D. Whitesell - Allentown PA, US
Jerry Pirog - Easton PA, US
Jonathan Kenny - Galway, IE
Joseph R. Hasting - Orefield PA, US
Narender Vangati - Austin TX, US
Stephen Miller - Round Rock TX, US
Te K. Ma - Allentown PA, US
William Burroughs - Macungie PA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/37
G06F 12/0811
G06F 13/16
G06F 9/54
G06F 12/0868

Abstract:

Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

US Patent:

20180365053, Dec 20, 2018

Filed:

Jun 19, 2017

Appl. No.:

15/626806

Inventors:

- Santa Clara CA, US
Jerry Pirog - Easton PA, US
Joseph R. Hasting - Orefield PA, US
Te K. Ma - Allentown PA, US

International Classification:

G06F 9/48

Abstract:

Apparatus and method for multi-core dynamically-balanced task processing while maintaining task order in chip multiprocessor platforms. One embodiment of an apparatus includes: a distribution circuitry to distribute, among a plurality of processing units, tasks from one or more workflows; a history list to track all tasks distributed by the distribution circuitry; an ordering queue to store one or more sub-tasks received from a first processing unit as a result of the first processing unit processing a first task; and wherein, responsive to a detection that all sub-tasks of the first task have been received and that the first task is the oldest task for a given parent workflow tracked by the history list, all sub-tasks associated with the first task are to be placed in a replay queue to be replayed in the order in which each sub-task was received.

US Patent:

20170286337, Oct 5, 2017

Filed:

Mar 31, 2016

Appl. No.:

15/087154

Inventors:

Ren Wang - Portland OR, US
Yipeng Wang - Beaverton OR, US
Andrew Herdrich - Hillsboro OR, US
Tsung-Yuan Tai - Portland OR, US
Niall McDonnell - Limerick, IE
Stephen Van Doren - Portland OR, US
David Sonnier - Austin TX, US
Debra Bernstein - Sudbury MA, US
Hugh Wilkinson - Newton MA, US
Narender Vangati - Austin TX, US
Stephen Miller - Round Rock TX, US
Gage Eads - Austin TX, US
Andrew Cunningham - Ennis, IE
Jonathan Kenny - Co. Tipperary, IE
Bruce Richardson - Sixmilebridge, IE
William Burroughs - Macungie PA, US
Joseph Hasting - Orefield PA, US
An Yan - Orefield PA, US
James Clee - Orefield PA, US
Te Ma - Allentown PA, US
Jerry Pirog - Easton PA, US
Jamison Whitesell - Bethlehem PA, US

International Classification:

G06F 13/36
G06F 13/40
G06F 12/10
G06F 13/24

Abstract:

Technologies for a distributed hardware queue manager include a compute device having a procesor. The processor includes two or more hardware queue managers as well as two or more processor cores. Each processor core can enqueue or dequeue data from the hardware queue manager. Each hardware queue manager can be configured to contain several queue data structures. In some embodiments, the queues are addressed by the processor cores using virtual queue addresses, which are translated into physical queue addresses for accessing the corresponding hardware queue manager. The virtual queues can be moved from one physical queue in one hardware queue manager to a different physical queue in a different physical queue manager without changing the virtual address of the virtual queue.