Jerry M Soden

US Patent:

7525325, Apr 28, 2009

Filed:

Dec 18, 2006

Appl. No.:

11/640720

Inventors:

Mark W. Jenkins - Albuquerque NM, US
Paiboon Tangyunyong - Albuquerque NM, US
Jerry M. Soden - Placitas NM, US
Jeremy A. Walraven - Albuquerque NM, US
Alejandro A. Pimentel - Albuquerque NM, US

Assignee:

Sandia Corporation - Alburquerque NM

International Classification:

G01R 31/305
G01R 31/26
G01N 23/00

US Classification:

324751, 438 17, 250306, 250307, 250308, 250309, 250310

Abstract:

A passive voltage contrast (PVC) system and method are disclosed for analyzing ICs to locate defects and failure mechanisms. During analysis a device side of a semiconductor die containing the IC is maintained in an electrically-floating condition without any ground electrical connection while a charged particle beam is scanned over the device side. Secondary particle emission from the device side of the IC is detected to form an image of device features, including electrical vias connected to transistor gates or to other structures in the IC. A difference in image contrast allows the defects or failure mechanisms be pinpointed. Varying the scan rate can, in some instances, produce an image reversal to facilitate precisely locating the defects or failure mechanisms in the IC. The system and method are useful for failure analysis of ICs formed on substrates (e. g. bulk semiconductor substrates and SOI substrates) and other types of structures.

US Patent:

60313862, Feb 29, 2000

Filed:

Oct 31, 1997

Appl. No.:

8/962465

Inventors:

Edward I. Cole - Albuquerque NM
Jerry M. Soden - Placitas NM

Assignee:

Sandia Corporation - Albuquerque NM

International Classification:

G01R 3126

US Classification:

324765

Abstract:

An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V. sub. DD, to an IC under test and measures a transient voltage component, V. sub. DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V. sub. DDT signal can be used to distinguish between defective and defect-free (i. e. known good) ICs. The V. sub. DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

US Patent:

54303052, Jul 4, 1995

Filed:

Apr 8, 1994

Appl. No.:

8/225021

Inventors:

Edward I. Cole - Albuquerque NM
Jerry M. Soden - Placitas NM

Assignee:

The United States of America as represented by the United States
Department of Energy - Washington DC

International Classification:

G01N 2188

US Classification:

25055907

Abstract:

An apparatus and method are described for analyzing an integrated circuit (IC), The invention uses a focused light beam that is scanned over a surface of the IC to generate a light-induced voltage alteration (LIVA) signal for analysis of the IC, The LIVA signal may be used to generate an image of the IC showing the location of any defects in the IC; and it may be further used to image and control the logic states of the IC. The invention has uses for IC failure analysis, for the development of ICs, for production-line inspection of ICs, and for qualification of ICs.

US Patent:

58444165, Dec 1, 1998

Filed:

Nov 2, 1995

Appl. No.:

8/552184

Inventors:

Ann N. Campbell - Albuquerque NM
Jerry M. Soden - Placitas NM

Assignee:

Sandia Corporation - Albuquerque NM

International Classification:

G01R 31302

US Classification:

324750

Abstract:

An ion-beam apparatus and method for analyzing and controlling integrated circuits. The ion-beam apparatus comprises a stage for holding one or more integrated circuits (ICs); a source means for producing a focused ion beam; and a beam-directing means for directing the focused ion beam to irradiate a predetermined portion of the IC for sufficient time to provide an ion-beam-generated electrical input signal to a predetermined element of the IC. The apparatus and method have applications to failure analysis and developmental analysis of ICs and permit an alteration, control, or programming of logic states or device parameters within the IC either separate from or in combination with applied electrical stimulus to the IC for analysis thereof. Preferred embodiments of the present invention including a secondary particle detector and an electron floodgun further permit imaging of the IC by secondary ions or electrons, and allow at least a partial removal or erasure of the ion-beam-generated electrical input signal.