Jerry S Wang

US Patent:

20030066809, Apr 10, 2003

Filed:

Oct 9, 2001

Appl. No.:

09/973095

Inventors:

Jerry Wang - Paramus NJ, US

International Classification:

C02F001/00

US Classification:

210/800000

Abstract:

The invention provides a means for discharging sediments by carrying them with the main water streams being released to the hydropower generators without the aid of any external supplied energy or pump and without wasting the useful potential energy of the water. The method of this invention can also be used for collecting valuable underwater mineral sediments from reservoirs or mountain lakes. With the addition of a fluid drive assembly, the effluent discharge system of this invention also facilitates powering of underwater dredging equipment or other underwater machinery for underwater work.

US Patent:

44516126, May 29, 1984

Filed:

Sep 29, 1982

Appl. No.:

6/426402

Inventors:

Jerry C. Wang - Lodi NJ
Michael R. Stepanian - Ridgewood NJ

Assignee:

Mobil Oil Corporation - New York NY

International Classification:

C08F27902

US Classification:

525 53

Abstract:

The present invention relates to a method for the production of high impact polystyrene utilizing a continuous process in place of the previously known batch polymerization techniques. The continuous process includes the steps of rubber solution preparation; prepolymerization; second stage polymerization; devolatilization and separation extrusion and pelletizing.

US Patent:

57650276, Jun 9, 1998

Filed:

Sep 26, 1994

Appl. No.:

8/310298

Inventors:

Jerry Borjeng Wang - Lake Forest CA
Robert Vernon Harper - Torrance CA
Chih-Chung Shi - Yorba Linda CA

Assignee:

Toshiba American Information Systems, Inc. - Irvine CA

International Classification:

G06F 1300

US Classification:

395860

Abstract:

An application specific integrated circuit (ASIC)/field programmable gate array (FPGA) which is a component of a wireless LAN controller including a local processor and a memory enables the controller to interface with both PCMCIA. TM. and AT. TM. host computer systems. The ASIC/FPGA enables communication between a radio frequency communication module, a local processor, and the host computer. The ASIC/FPGA also includes a throttle feature that decreases the access of the host computer in comparison to access of the local processor in order to enable the local processor to rapidly generate an acknowledge signal as required by various RF LAN specifications. During operation of the controller, data to be transmitted by the host computer onto the network is written by the host to an SRAM via the ASIC/FPGA, and the host commands the local processor via the ASIC/FPGA to forward the transmitted data to the RF communication module. Under the control of the ASIC/FPGA, the local processor then forwards the transmit data from the SRAM to the RF communication module. When data is received from the RF communication module, the local processor, under the control of the ASIC/FPGA, receives the data and stores the received data in the SRAM.