Jessica Chen

US Patent:

20220351759, Nov 3, 2022

Filed:

May 3, 2021

Appl. No.:

17/306562

Inventors:

- Boise ID, US
Nevil N. Gajera - Meridian ID, US
Jessica Chen - Boise ID, US
Lingming Yang - Meridian ID, US

International Classification:

G11C 7/10

Abstract:

Methods, systems, and devices for dynamic read voltage techniques are described. In some examples, a memory device may include one or more partitions made up of multiple disjoint subsets of memory arrays. The memory device may receive a read command to read the one or more partitions and enter a drift determination phase. During the drift determination phase, the memory device may concurrently apply a respective voltage of a set of voltages to each disjoint subset and determine a quantity of memory cells in each disjoint subset that have a threshold voltage below the applied voltage. Based on a comparison between the determined quantity of memory cells and a predetermined quantity of memory cells, the memory device may select a voltage from the set of voltages and utilize the selected voltage to read the one or more partitions.

US Patent:

20220284973, Sep 8, 2022

Filed:

May 26, 2022

Appl. No.:

17/825941

Inventors:

- Boise ID, US
Xuan-Anh Tran - Boise ID, US
Jessica Chen - Boise ID, US
Jason A. Durand - Boise ID, US
Nevil N. Gajera - Meridian ID, US
Yen Chun Lee - Boise ID, US

International Classification:

G11C 16/34
G11C 16/30
G11C 16/26
G11C 16/10

Abstract:

Methods, systems, and devices for accessing a multi-level memory cell are described. The memory device may perform a read operation that includes pre-read portion and a read portion to access the multi-level memory cell. During the pre-read portion, the memory device may apply a plurality of voltages to a plurality of memory cells to identify a likely distribution of memory cells storing a first logic state. During the read portion, the memory device may apply a first read voltage to a memory cell based on performing the pre-read portion. The memory device may apply a second read voltage to the memory cell during the read portion that is based on the first read voltage. The memory device may determine the logic state stored by the memory cell based on applying the first read voltage and the second read voltage.

US Patent:

20230060231, Mar 2, 2023

Filed:

Oct 26, 2022

Appl. No.:

18/049855

Inventors:

- Boise ID, US
Fabio Pellizzer - Boise ID, US
Jessica Chen - Boise ID, US
Nevil Gajera - Meridian ID, US

International Classification:

G11C 13/00

Abstract:

Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.

US Patent:

20210151107, May 20, 2021

Filed:

Nov 4, 2020

Appl. No.:

17/089146

Inventors:

- Boise ID, US
Mingdong Cui - Folsom CA, US
Joseph M. McCrate - Boise ID, US
Karthik Sarpatwari - Boise ID, US
Jessica Chen - Boise ID, US

International Classification:

G11C 13/00
H01L 45/00
G11C 5/14

Abstract:

Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.

US Patent:

20210057026, Feb 25, 2021

Filed:

Aug 19, 2019

Appl. No.:

16/544669

Inventors:

- Boise ID, US
Fabio Pellizzer - Boise ID, US
Jessica Chen - Boise ID, US
Nevil Gajera - Meridian ID, US

International Classification:

G11C 13/00

Abstract:

Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.

US Patent:

20210005254, Jan 7, 2021

Filed:

Jul 2, 2019

Appl. No.:

16/460863

Inventors:

- Boise ID, US
Mingdong Cui - Folsom CA, US
Joseph M. McCrate - Boise ID, US
Karthik Sarpatwari - Boise ID, US
Jessica Chen - Boise ID, US

International Classification:

G11C 13/00
H01L 45/00
G11C 5/14

Abstract:

Methods, systems, and devices for memory cell selection to enable a memory device to select a targeted memory cell during a write operation are described. The memory device may apply a first pulse to a selected bit line of the targeted memory cell while applying a voltage to deselected word lines to prevent current leakage. If the targeted memory is not selected after the first pulse, the memory device may apply a second pulse to the selected bit line while applying a voltage to the deselected word lines. If the targeted memory cell is not selected following the second pulse, the memory device may apply a third pulse to the selected bit line while applying the voltage to the deselected word lines. The memory device may detect a snapback event after any of the pulses if the targeted memory cell is selected.