Jia Ning Chen

US Patent:

6927454, Aug 9, 2005

Filed:

Oct 7, 2003

Appl. No.:

10/680820

Inventors:

Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L029/76

US Classification:

257336, 257 19, 257 20, 257 24, 257192, 257213, 257344, 257392

Abstract:

A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

US Patent:

7378336, May 27, 2008

Filed:

May 9, 2005

Appl. No.:

11/124978

Inventors:

Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/3205

US Classification:

438592, 438593, 257413

Abstract:

A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4 A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

US Patent:

7465649, Dec 16, 2008

Filed:

Aug 30, 2007

Appl. No.:

11/847384

Inventors:

Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/3205

US Classification:

438592, 438593, 257413

Abstract:

A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4 A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

US Patent:

7666775, Feb 23, 2010

Filed:

Apr 17, 2008

Appl. No.:

12/104570

Inventors:

Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US

Assignee:

International Businesss Machines Corporation - Armonk NY

International Classification:

H01L 21/3205

US Classification:

438592, 438593, 257413

Abstract:

A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4 A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

US Patent:

20200083398, Mar 12, 2020

Filed:

Nov 13, 2019

Appl. No.:

16/681974

Inventors:

- Armonk NY, US
Devendra Sadana - Pleasantville NY, US
Stephen W. Bedell - Wappingers Falls NY, US
Bruce Doris - Slingerlands NY, US
Hariklia Deligianni - Alpine NJ, US
Jia Chen - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 33/00
H01L 27/15
H01L 33/62
H01L 33/40
H01L 33/32

Abstract:

A semiconductor device includes a substrate and a buffer layer disposed on a first portion, a second portion, and a third portion of the substrate. The semiconductor device further includes a multilayer light-emitting diode (LED) stack disposed on the first portion of the substrate, and an optical sensor disposed on the second portion of the substrate. The semiconductor device further includes at least one electrode disposed on the third portion of the substrate, a first conductor in contact with the multilayer LED stack, and a second conductor in contact with the optical sensor. The at least one electrode, the first conductor, and the second conductor are formed of a glassy carbon material.

US Patent:

20200084498, Mar 12, 2020

Filed:

Nov 12, 2019

Appl. No.:

16/681274

Inventors:

- Armonk NY, US
Jia CHEN - New York NY, US
Sarbajit K. Rakshit - Kolkata, IN
Craig M. TRIM - Ventura CA, US

International Classification:

H04N 21/422
H04N 5/44
H04N 21/439
H04N 21/488
H04N 21/442

Abstract:

Systems and methods for a cognitive display control are disclosed. A method includes: obtaining, by a computer device, context information of current content being displayed on a display; generating, by the computer device, a respective attention score for each one of plural users for the current content; receiving, by the computer device, input to change from the current content to new content; determining, by the computer device and based on the receiving, that the attention score of at least one of the plural users exceeds a threshold value; and controlling the display, by the computer device and based on the determining, to display an alert and a prompt to confirm or reject changing to the new content.

US Patent:

20200044113, Feb 6, 2020

Filed:

Jul 31, 2018

Appl. No.:

16/050989

Inventors:

- Armonk NY, US
Devendra Sadana - Pleasantville NY, US
Stephen W. Bedell - Wappingers Falls NY, US
Bruce Doris - Slingerlands NY, US
Hariklia Deligianni - Alpine NJ, US
Jia Chen - New York NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 33/00
H01L 33/40
H01L 33/62
H01L 27/15
H01L 33/32

Abstract:

A semiconductor device includes a substrate and a buffer layer disposed on a first portion, a second portion, and a third portion of the substrate. The semiconductor device further includes a multilayer light-emitting diode (LED) stack disposed on the first portion of the substrate, and an optical sensor disposed on the second portion of the substrate. The semiconductor device further includes at least one electrode disposed on the third portion of the substrate, a first conductor in contact with the multilayer LED stack, and a second conductor in contact with the optical sensor. The at least one electrode, the first conductor, and the second conductor are formed of a glassy carbon material.

US Patent:

20180089198, Mar 29, 2018

Filed:

Apr 10, 2017

Appl. No.:

15/483929

Inventors:

- San Francisco CA, US
David NATHANSON - Astoria NY, US
Jia CHEN - Foster City CA, US
Luke BALL - Berkeley CA, US
Shankara B. SUBRAMANYA - Sunnyvale CA, US
Kanishka MAHESHWARI - San Francisco CA, US
Susan KIMBERLIN - San Francisco CA, US

Assignee:

salesforce.com, inc. - San Francisco CA

International Classification:

G06F 17/30

Abstract:

A method of establishing personalized limits on a search responsive to a key word query in an enterprise search system is described that includes receiving an object types access history for a particular user. Applying this method, the object types access history includes records of object types selected from search results returning multiple object types and records of object types selected via interfaces other than search results. The method continues with determining and storing in computer readable memory a personalized scope of object types. The personalized scope of object types sets a limit on object types initially returned by an enterprise search system for the particular user in response to key word queries by the particular user that do not specify object types to search.