Jia Chen

US Patent:

6927454, Aug 9, 2005

Filed:

Oct 7, 2003

Appl. No.:

10/680820

Inventors:

Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L029/76

US Classification:

257336, 257 19, 257 20, 257 24, 257192, 257213, 257344, 257392

Abstract:

A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

US Patent:

7008547, Mar 7, 2006

Filed:

Mar 7, 2003

Appl. No.:

10/383380

Inventors:

Jia Ming Chen - Plainsboro NJ, US
Yongchi Tian - Princeton NJ, US
Zilan Shen - West Windsor NJ, US
Pradyumna Swain - Franklin Park NJ, US

Assignee:

Sarnoff Corporation - Princeton NJ

International Classification:

B44C 1/22
H01B 13/00
H01L 21/461
G01N 15/06
G01N 27/00

US Classification:

216 11, 216 13, 216 16, 216 41, 216 56, 216 58, 216 72, 216 74, 422 50, 422 681, 422 8201, 422 83, 422 98, 436 43, 436149, 436151, 73 101, 73 102, 438 21, 438400, 438689, 438735, 29592, 295921

Abstract:

Provided is a solid phase array of electrical sensors, each comprising a channel and electrical leads for attaching to a voltage, current or resistivity meter for measuring the voltage, current or resistivity through the pore, wherein the channels are formed of a single substrate.

US Patent:

7378336, May 27, 2008

Filed:

May 9, 2005

Appl. No.:

11/124978

Inventors:

Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/3205

US Classification:

438592, 438593, 257413

Abstract:

A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4 A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

US Patent:

7465649, Dec 16, 2008

Filed:

Aug 30, 2007

Appl. No.:

11/847384

Inventors:

Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/3205

US Classification:

438592, 438593, 257413

Abstract:

A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4 A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

US Patent:

7666775, Feb 23, 2010

Filed:

Apr 17, 2008

Appl. No.:

12/104570

Inventors:

Kevin K. Chan - Staten Island NY, US
Jia Chen - Ossining NY, US
Shih-Fen Huang - Bedford Corners NY, US
Edward J. Nowak - Essex Junction VT, US

Assignee:

International Businesss Machines Corporation - Armonk NY

International Classification:

H01L 21/3205

US Classification:

438592, 438593, 257413

Abstract:

A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiOor SiGeOinterfacial layer of 3 to 4 A thick. The thin SiOor SiGeOinterfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.

US Patent:

20020110220, Aug 15, 2002

Filed:

Nov 20, 2001

Appl. No.:

09/989746

Inventors:

Zilan Shen - West Windsor NJ, US
Jia Chen - Plainsboro NJ, US
Heinz Busta - Park Ridge IL, US
Steven Lipp - Cranbury NJ, US

International Classification:

H01J035/08

US Classification:

378/124000, 378/092000

Abstract:

A method and apparatus for delivering localized x-ray radiation to the interior of a body includes a plurality of x-ray sources disposed in a distal portion of a flexible catheter shaft. The plurality of x-ray sources are secured to a flexible cord disposed longitudinally throughout at least a portion of the shaft. The plurality of x-ray sources are electrically coupled to a control circuit for activating specific ones of the plurality of x-ray sources in order to customize the irradiation of the interior of the body.

US Patent:

20200163696, May 28, 2020

Filed:

Nov 26, 2018

Appl. No.:

16/200193

Inventors:

- Armonk NY, US
Bruce B. Doris - Slingerlands NY, US
Devendra K. Sadana - Pleasantville NY, US
Stephen W. Bedell - Wappingers Falls NY, US
Jia Chen - New York NY, US
Hariklia Deligianni - Alpine NJ, US

International Classification:

A61B 17/34
G16H 20/40
C12N 5/07
A61B 5/00

Abstract:

An access system having a communication component that interfaces with a first device and a second device, where the first device is located inside or on an entity and coupled to a biological organism of the entity, and where the second device is located outside the entity and a controller component that controls a function of the first device, employing the communication component, to provide treatment to the biological organism of the entity coupled to the first device based on a request received from the second device.

US Patent:

20200164222, May 28, 2020

Filed:

Nov 26, 2018

Appl. No.:

16/199627

Inventors:

- Armonk NY, US
Stephen W. Bedell - Wappingers Falls NY, US
Jia Chen - New York NY, US
Hariklia Deligianni - Alpine NJ, US
Devendra K. Sadana - Pleasantville NY, US

International Classification:

A61N 5/06
A61B 5/04
C30B 25/02
H01L 21/02

Abstract:

Embodiments of the invention are directed to an integrated optogenetic device. The integrated optogenetic includes a substrate layer having a first substrate region and a second substrate region. The device further includes a first contact formed over the substrate layer in the first substrate region and a second contact layer formed over the substrate layer in the second region. In addition, the device includes a light-emitting diode (LED) structure communicatively coupled to the first contact layer and a biosensor element communicatively coupled to the second contact layer. The first contact layer is configured to operate as a bottom contact that provides electrical contact to the LED structure. The first contact layer is further configured to be substantially lattice matched with the substrate layer and a bottom layer of the LED structure.