Jiang Jie Li

US Patent:

6628545, Sep 30, 2003

Filed:

Nov 26, 2002

Appl. No.:

10/306080

Inventors:

Jiang Li - San Jose CA
Yider Wu - Campbell CA
Zhizheng Liu - Sunnyvale CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518505, 36518518, 36518521, 36518529, 3651853

Abstract:

A memory circuit employed in a memory device is disclosed. According to one embodiment, the memory circuit comprises a first memory cell and a second memory cell. The first memory cell has a drain terminal connected to a bit line, which is connected to a sensing circuit. The first memory cell also has a control gate connected to a word line. The second memory cell also has a drain terminal connected to the bit line. The second memory cell has its control gate coupled to ground. The memory circuit supplies a source voltage greater than a ground voltage to a source terminal of the first memory cell and to a source terminal of the second memory cell such that the gate-to-source voltage of the second memory cell is less than the threshold voltage of the second memory cell.

US Patent:

6643185, Nov 4, 2003

Filed:

Aug 7, 2002

Appl. No.:

10/215140

Inventors:

Zhigang Wang - Santa Clara CA
Nian Yang - San Jose CA
Jiang Li - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

3651853, 36518527

Abstract:

A method for repairing over-erasure of floating gate memory devices. Specifically, one embodiment of the present invention discloses a method for performing a program disturb operation on an array of memory cells for repairing over-erasure of fast bits. The program disturb operation is applied simultaneously to the entire array making it compatible with channel erase schemes. The fast bits are programmed back to a normal state above 0 Volts by applying a substrate voltage to a substrate common to the array of memory cells. A gate voltage is applied to a plurality of word lines coupled to control gates of said array of memory cells. A program pulse time for applying voltages ranges from approximately 10 microseconds to 1 second. A voltage differential between a control gate and the substrate in a memory cell is in the range of approximately 9 Volts to about 20 Volts.

US Patent:

6654285, Nov 25, 2003

Filed:

Feb 27, 2002

Appl. No.:

10/083789

Inventors:

Richard Fastow - Cupertino CA
Jiang Li - San Jose CA
Lee Cleveland - Santa Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1134

US Classification:

3651852, 36518522

Abstract:

In a method of reading a memory cell of a memory cell array, electrical potentials are applied to a conductive structure connected to the drain, a conductive structure connected to the source, and the gate of the transistor of a cell to be read. Electrical potential are also applied to a conductive structure connected to the drain, a conductive structure connected to the source, and the gate of the transistor of a reference cell, providing current through the reference cell. The level of resistance to current through the reference cell is chosen by selecting the level of resistance in the conductive structure connected to the source of the transistor of the reference cell.

US Patent:

6717850, Apr 6, 2004

Filed:

Dec 5, 2002

Appl. No.:

10/313676

Inventors:

Jiang Li - San Jose CA
Nian Yang - San Jose CA
Zhigang Wang - Santa Clara CA
John Jianshi Wang - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518509, 36518518, 36518529, 36518533

Abstract:

A method of processing a semiconductor device is disclosed and comprises applying a relatively high voltage across a gate stack of a flash memory cell for a certain period of time. Then, the polarity of the applied voltage is reversed and is again applied across the gate stack for another certain period of time. The voltage applied is greater than a channel erase voltage utilized for the memory cell. This applied voltage causes extrinsic defects to become amplified at interfaces of oxide/insulator layers of the gate stack. Then, the memory cell is tested (e. g. , via a battery of tests) in order to determine if the memory cell is defective. If the cell is defective (e. g. , fails the test), it can be assumed that substantial extrinsic defects were present in the memory cell and have been amplified resulting in the test failure. If the cell passes the test, it can be assumed that the memory cell is substantially free from extrinsic defects. Defective memory cells/devices can be marked or otherwise indicated as being defective.

US Patent:

6754106, Jun 22, 2004

Filed:

Sep 16, 2002

Appl. No.:

10/245146

Inventors:

Yider Wu - San Jose CA
Jean Yang - Sunnyvale CA
Jiang Li - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1606

US Classification:

3651852, 36518521, 36518524

Abstract:

A load circuit for compensating for source side loading effects in a non-volatile memory. Specifically, embodiments of the present invention describe a reference cell that is coupled to a plurality of load circuits. At least one of the plurality of load circuits, an m load circuit, comprises a select transistor coupled to m resistors that are coupled in series. The m load circuit matches a source side loading effect of a corresponding m memory cell located m memory cells away from a source line node on a source line coupling source regions in memory cells of a row of memory cells.

US Patent:

6765827, Jul 20, 2004

Filed:

Mar 10, 2003

Appl. No.:

10/384936

Inventors:

Jiang Li - San Jose CA
Lee Cleveland - Santa Clara CA
Ming Kwan - San Leandro CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1606

US Classification:

36518509, 365200, 365201

Abstract:

In a method and system for detecting defective material surrounding a flash memory cell, stressing voltage is applied between a control gate and a well of the flash memory cell. A stress recovery process is then performed on the flash memory cell. Any short circuit, formed through the material between the control gate and at least one of drain and source bit line junctions of the flash memory cell, is detected. The material surrounding the flash memory cell may be an inter-level dielectric material. The present invention may be applied to an array of flash memory cells comprising a flash memory device during testing of the flash memory device before being shipped to the customer.

US Patent:

6797650, Sep 28, 2004

Filed:

Jan 14, 2003

Appl. No.:

10/342032

Inventors:

Zhigang Wang - Santa Clara CA
Nian Yang - San Jose CA
John Jianshi Wang - San Jose CA
Jiang Li - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2131

US Classification:

438786, 438769

Abstract:

One aspect of the invention relates to flash memory device that stores charge in a substantially stoichiometric silicon oxynitride dielectric. A stoichiometric silicon oxynitride dielectric can be represented by the formula (Si N ) (SiO ) , where x is from 0-1. A substantially stoichiometric silicon oxynitride dielectric has relatively few atoms that do not fit into the foregoing formula. The flash memory devices of the present invention have fewer defects and lower leakage than comparable SONOS-type flash memory devices. Another aspect of the invention relates to assessing the stoichiometry by FTIR, refractive index measurement, or a combination of the two.

US Patent:

7073104, Jul 4, 2006

Filed:

Mar 10, 2003

Appl. No.:

10/384856

Inventors:

Jiang Li - San Jose CA, US
Richard Fastow - Cupertino CA, US
Steve Tam - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 29/00

US Classification:

714718, 36518519

Abstract:

In a method and system for applying a testing voltage signal, a voltage source generates the testing voltage signal that ramps from an initial voltage to an intermediate voltage with a first ramping rate. In addition, the testing voltage then ramps from the intermediate voltage to an end voltage with a second ramping rate, with the first ramping rate being greater than the second ramping rate. The present invention may be applied to particular advantage when the testing voltage signal is applied on a control gate of a flash memory cell for channel erasure of the flash memory cell. In this manner, the testing voltage signal ramps to the end voltage with reduced time for minimizing testing time.