Jiang Jen Lin

US Patent:

20120198172, Aug 2, 2012

Filed:

Apr 11, 2012

Appl. No.:

13/444439

Inventors:

Jiang Lin - Austin TX, US
Lixin Zhang - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/08

US Classification:

711129, 711130, 711E12038

Abstract:

A mechanism is provided in a virtual machine monitor for providing cache partitioning in virtualized environments. The mechanism assigns a virtual identification (ID) to each virtual machine in the virtualized environment. The processing core stores the virtual ID of the virtual machine in a special register. The mechanism also creates an entry for the virtual machine in a partition table. The mechanism may partition a shared cache using a vertical (way) partition and/or a horizontal partition. The entry in the partition table includes a vertical partition control and a horizontal partition control. For each cache access, the virtual machine passes the virtual ID along with the address to the shared cache. If the cache access results in a miss, the shared cache uses the partition table to select a victim cache line for replacement.

US Patent:

20110055827, Mar 3, 2011

Filed:

Aug 25, 2009

Appl. No.:

12/546791

Inventors:

Jiang Lin - Austin TX, US
Lixin Zhang - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/08
G06F 9/455

US Classification:

718 1, 711129, 711130, 711E12017

Abstract:

A mechanism is provided in a virtual machine monitor for providing cache partitioning in virtualized environments. The mechanism assigns a virtual identification (ID) to each virtual machine in the virtualized environment. The processing core stores the virtual ID of the virtual machine in a special register. The mechanism also creates an entry for the virtual machine in a partition table. The mechanism may partition a shared cache using a vertical (way) partition and/or a horizontal partition. The entry in the partition table includes a vertical partition control and a horizontal partition control. For each cache access, the virtual machine passes the virtual ID along with the address to the shared cache. If the cache access results in a miss, the shared cache uses the partition table to select a victim cache line for replacement.

US Patent:

20200334160, Oct 22, 2020

Filed:

Apr 19, 2019

Appl. No.:

16/389135

Inventors:

- Sichuan Province, CN
Leigang Kou - Austin TX, US
Jiang Lin - Austin TX, US
Jing Li - Sichuan, CN
Zehan Cui - Sichuan, CN

International Classification:

G06F 12/0871
G06K 9/62
G06F 9/50
G06F 11/30

Abstract:

A cache management method for a computing device, a cache controller, a processor and a processor readable storage medium are disclosed. The cache management method for the computing device includes classifying a workload on a cache based on a cache architecture of the computing device, characteristics of a cache level of the cache and a difference in the workload on the cache, and configuring a priority for the classified workload; and allocating a cache resource and performing cache management according to the configured priority.

US Patent:

20200272573, Aug 27, 2020

Filed:

Feb 22, 2019

Appl. No.:

16/283284

Inventors:

- Chengdu, CN
Ruchir Dalal - Austin TX, US
Feng Zeng - Chengdu, CN
Jiang Lin - Austin TX, US

International Classification:

G06F 12/1009
G06F 12/02
G06F 12/14
G06F 9/455

Abstract:

This disclosure provides a method for tagging control information associated with a physical address in a processing system, including setting a hardware tag for the control information, the hardware tag being invisible to a software system in the processing system; joining the hardware tag with the physical address to form a compound physical address, the hardware tag including M bits carried by a dedicated hardware tag control line, the physical address including N bits carried by a physical address bus, M and N being positive integers; and tagging the control information with the hardware tag in the compound physical address.

US Patent:

20150200002, Jul 16, 2015

Filed:

Dec 4, 2014

Appl. No.:

14/560674

Inventors:

Jiang LIN - Austin TX, US
Matthew Garrett - Austin TX, US

International Classification:

G11C 7/10
G06F 12/10
G11C 11/406

Abstract:

Efficiently tracking activations to rows of memory using a reduced number of row activation counters that indicate whether a memory row is activated during an activation period and row activation counters that indicate a number of permitted activations to a memory row within a maximum activation window.