Jibin Han

US Patent:

7370310, May 6, 2008

Filed:

Aug 8, 2005

Appl. No.:

11/200454

Inventors:

Milan R. Saini - Palo Alto CA, US
Jibin Han - Albuquerque NM, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

G06F 17/50
H03K 17/693

US Classification:

716 16, 716 4, 716 17, 716 18

Abstract:

Address map generation is described. More particularly, static addresses are obtained. A system design at least a portion of which is for instantiation in configurable logic of an integrated circuit is obtained. The system design includes a processor. At least one predefined circuit block in the design is identified as a peripheral connected to a processor. The at least one predefined circuit block is for instantiation in the configurable logic of the integrated circuit. Assigned to the at least one predefined circuit block is a static address range which is obtained from the static addresses. An address map for the design is generated having the at least one predefined circuit block with the static address range. Thus, for example, independent designers designing separate systems having a same set of peripherals may map to the same static address ranges independent of software system builder tool version, board, or processor used.

US Patent:

8359557, Jan 22, 2013

Filed:

May 3, 2011

Appl. No.:

13/100013

Inventors:

Xi Chen - Santa Clara CA, US
Jibin Han - Longmont CO, US
Paulo L. Dutra - San Jose CA, US
Thien Than - Thornton CO, US
Biping Wu - Longmont CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716101, 716106

Abstract:

A method is provided for generation of a circuit design. A plurality of components, including at least a processor and a peripheral device, is instantiated in a circuit design. One or more parameterizable data bus interface blocks are automatically selected based on the master-slave relationships, requirements, and capabilities of the components. The one or more parameterizable data bus interface blocks are instantiated in the circuit design. In response to user input, values are assigned to one or more parameters of the processor. The plurality of components and data bus interface blocks are automatically parameterized by determining appropriate parameter values according to the parameters of the processor and capabilities and requirements of the components and data bus interface blocks.