Jie Chen

US Patent:

7026695, Apr 11, 2006

Filed:

Nov 19, 2003

Appl. No.:

10/718482

Inventors:

Xiao Yang - Sunnyvale CA, US
Shoucheng Zhang - Stanford CA, US
Dongmin Chen - Sunnyvale CA, US
Jie Chen - Saratoga CA, US

Assignee:

Miradia Inc. - Sunnyvale CA

International Classification:

H01L 27/14

US Classification:

257414, 257515, 438 52

Abstract:

An electro-mechanical system, the system comprising a first surface with an electrically activated electrode coupled to the first surface and to an electrical source to receive a first signal. The system further comprising a moveable structure suspended at a first height over the first surface, the moveable structure being attracted toward the electrode based upon the first signal, and the moveable structure being attracted toward the first surface through an interaction with one or more parasitic forces. The systems also provides a landing post coupled to the moveable structure, the landing post being adapted to contact the base of the landing post against the first surface when the electrically activated electrode receives a predetermined voltage bias associated with the first signal, thereby maintaining an outer portion of the moveable structure free from physical contact with the first surface and reducing a magnitude of one or more parasitic forces.

US Patent:

7358772, Apr 15, 2008

Filed:

Feb 28, 2005

Appl. No.:

11/069921

Inventors:

Jie Chen - Saratoga CA, US
Ting-Yen Chiang - Palo Alto CA, US
Kuang-Yu Chen - Saratoga CA, US
Chen Yu Wang - San Jose CA, US
Joe Froniewski - Palo Alto CA, US

Assignee:

Silego Technology, Inc. - Santa Clara CA

International Classification:

H03K 19/0175

US Classification:

326 83, 326 27

Abstract:

A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

US Patent:

7612580, Nov 3, 2009

Filed:

Feb 15, 2008

Appl. No.:

12/070374

Inventors:

Jie Chen - Saratoga CA, US
Ting-Yen Chiang - Palo Alto CA, US
Kuang-Yu Chen - Saratoga CA, US
Chen Yu Wang - San Jose CA, US
Joe Froniewski - Palo Alto CA, US

Assignee:

Silego Technology, Inc. - Santa Clara CA

International Classification:

H03K 19/0175

US Classification:

326 30, 326 27

Abstract:

A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

US Patent:

7749361, Jul 6, 2010

Filed:

Jun 2, 2006

Appl. No.:

11/445690

Inventors:

Jie Chen - Saratoga CA, US
Peijun Ding - Saratoga CA, US
Suraj Rengarajan - San Jose CA, US
Ling Chen - Sunnyvale CA, US
Tram Vo - Milpitas CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 14/34

US Classification:

20419217, 20429812, 438687

Abstract:

A method of sputtering a copper seed layer and the target used therewith. The copper included in the sputtering target includes a first dopant reactive with copper and a second dopant unreactive with copper. Examples of the first dopant include Ti, Mg, and Al. Examples of the second dopant include Pd, Sn, In, Ir, and Ag. The amount of the first dopant may be determined by testing stress migration and that of the second dopant by testing electromigration.

US Patent:

8138785, Mar 20, 2012

Filed:

Sep 18, 2009

Appl. No.:

12/586288

Inventors:

Jie Chen - Saratoga CA, US
Ting-Yen Chiang - Palo Alto CA, US
Kuang-Yu Chen - Saratoga CA, US
Chen Yu Wang - San Jose CA, US
Joe Froniewski - Palo Alto CA, US

Assignee:

Silego Technology, Inc. - Santa Clara CA

International Classification:

H03K 19/0175

US Classification:

326 30, 326 27

Abstract:

A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

US Patent:

8498343, Jul 30, 2013

Filed:

Aug 16, 2010

Appl. No.:

12/806538

Inventors:

Jie Chen - San Jose CA, US
Keshab K. Parhi - Maple Grove MN, US

Assignee:

Leanics Corporation - Maple Grove MN

International Classification:

H04B 14/04

US Classification:

375242, 375219, 375229

Abstract:

The present invention relates to data processing techniques in multi-channel data transmission systems. In this invention, a method to efficiently deal with FEXT is proposed and a circuit architecture to implement the proposed MIMO-THP equalizer is developed for the application of high/ultra-high speed Ethernet systems. The proposed method relies on the fact that FEXT inherently contains information about the symbols transmitted from the far end transmitters and it can be viewed as a signal rather than noise. Compared with the traditional FEXT cancellation approaches, the proposed design inherits both advantages of MIMO equalization technique and TH precoding technique, thus having better performance. Unlike the existing MIMO-THP technology, the proposed design completely removes the feedback loops in the existing MIMO-THP architecture. Therefore, pipelining techniques can be easily applied to obtain a high-speed design of a multi-channel DSP transceiver.

US Patent:

8600039, Dec 3, 2013

Filed:

Aug 16, 2010

Appl. No.:

12/806539

Inventors:

Jie Chen - San Jose CA, US
Keshab K. Parhi - Maple Grove MN, US

Assignee:

Leanics Corporation - Maple Grove MN

International Classification:

H04M 9/08

US Classification:

37940609, 3794061, 37940611, 37940613, 37940614

Abstract:

The present invention relates to design and implementation of low complexity adaptive echo and NEXT cancellers in multi-channel data transmission systems. In this invention, a highly efficient weight update scheme is proposed to reduce the computational cost of the weight update part in adaptive echo and NEXT cancellers. Based on the proposed scheme, the hardware complexity of the weight update part can be further reduced by applying the word-length reduction technique. The proposed scheme is general and suitable for real applications such as design of a low complexity transceiver in 10GBase-T. Different with prior work, this invention considers the complexity reduction in weight update part of the adaptive filters such that the overall complexity of these adaptive cancellers can be significantly reduced.

US Patent:

20040207924, Oct 21, 2004

Filed:

Jan 12, 2004

Appl. No.:

10/756809

Inventors:

Jie Chen - Saratoga CA, US

Assignee:

XHP Microsystems, Inc. - Santa Clara CA

International Classification:

G02B027/14

US Classification:

359/634000

Abstract:

A color separation method and system wherein an optical spectrum is separated into optical wavelength ranges and wherein the optical signals of the separated wavelength ranges are further separated temporally. The optical spectrum can be spatially dispersed and the optical signals can be temporally dispersed, with three optical signals representing primary colors, such as red, green and blue.