Jie K Chen

US Patent:

8178699, May 15, 2012

Filed:

Jul 30, 2008

Appl. No.:

12/183032

Inventors:

Eric C Anderson - Irving TX, US
Ronald J Biediger - Houston TX, US
Jie Chen - Houston TX, US
Brian Dupre - Houston TX, US
Pedro Lory - Antwerp, BE
Robert V. Market - Pearland TX, US
Keith A. Monk - League City TX, US
Michael M. Savage - Pearland TX, US
Reginald Tennyson - Missouri City TX, US
Brandon M. Young - Germantown TN, US

Assignee:

Pfizer Inc. - New York NY

International Classification:

C07D 333/56

US Classification:

549 57

Abstract:

Provided are compounds that are modulators of CCR9 receptor activity, compositions containing the compounds and methods of use of the compounds and compositions. In certain embodiments, provided are methods for treating or ameliorating diseases associated with modulation of CCR9 receptor activity.

US Patent:

20220384353, Dec 1, 2022

Filed:

Oct 13, 2021

Appl. No.:

17/500086

Inventors:

- Dallas TX, US
Rajen Manicon Murugan - Dallas TX, US
Liang Wan - Chengdu, CN
Makarand Ramkrishna Kulkarni - Dallas TX, US
Jie Chen - Plano TX, US
Steven Alfred Kummerl - Carrollton TX, US

International Classification:

H01L 23/538
H01L 23/00
H01L 21/48

Abstract:

A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.

US Patent:

20230101847, Mar 30, 2023

Filed:

Sep 30, 2021

Appl. No.:

17/491378

Inventors:

- Dallas TX, US
Yiqi TANG - Allen TX, US
Rajen Manicon MURUGAN - Dallas TX, US
Jie CHEN - Plano TX, US
Tianyi LUO - Allen TX, US

International Classification:

H01L 25/065
H01L 23/31
H01L 23/00
H01L 23/498
H01L 25/00
H01L 21/56

Abstract:

In examples, a semiconductor package comprises a substrate and multiple columns of semiconductor dies positioned approximately in parallel along a length of the substrate. The package also includes multiple passive components positioned between the multiple columns of semiconductor dies, the multiple passive components angled between 30 and 60 degrees relative to the length of the substrate, a pair of the multiple passive components having a gap therebetween that is configured to permit mold compound flow through capillary action. The package also includes a mold compound covering the substrate, the multiple columns of semiconductor dies, and the multiple passive components.

US Patent:

20230021179, Jan 19, 2023

Filed:

Jul 19, 2021

Appl. No.:

17/379549

Inventors:

- Dallas TX, US
Rajen Manicon Murugan - Dallas TX, US
Chittranjan Mohan Gupta - Richardson TX, US
Jie Chen - Plano TX, US

International Classification:

H01L 49/02
H01F 17/00
H05K 3/46
H05K 1/11
H02M 3/158

Abstract:

A semiconductor device includes a die having an input port and an output port. The semiconductor device also includes a multilayer package substrate with pads on a surface of the multilayer package substrate configured to be coupled to circuit components of a printed circuit board. The multilayer package substrate also includes a passive filter comprising an input port and an output port, and a planar inductor. The planar inductor is coupled to a given pad of the pads of the multilayer package substrate with a first via of the multilayer package substrate and to the input port of the die with a second via of the multilayer package substrate. The planar inductor extends parallel to the surface of the multilayer package substrate.

US Patent:

20210159403, May 27, 2021

Filed:

Jan 6, 2021

Appl. No.:

17/142539

Inventors:

- Dallas TX, US
Yiqi Tang - Allen TX, US
Jie Chen - Dallas TX, US
Enis Tuncer - Dallas TX, US
Usman Mahmood Chaudhry - McKinney TX, US
Tony Ray Larson - Tucson AZ, US
Rajen Manicon Murugan - Dallas TX, US
John Paul Tellkamp - Rockwall TX, US
Satyendra Singh Chauhan - Murphy TX, US

International Classification:

H01L 43/14
H01L 43/06
G01R 15/20
H01L 23/495
G01R 33/07

Abstract:

A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

US Patent:

20200357987, Nov 12, 2020

Filed:

May 7, 2019

Appl. No.:

16/404978

Inventors:

- Dallas TX, US
Yiqi Tang - Allen TX, US
Jie Chen - Dallas TX, US
Enis Tuncer - Dallas TX, US
Usman Mahmood Chaudhry - McKinney TX, US
Tony Ray Larson - Tucson AZ, US
Rajen Manicon Murugan - Dallas TX, US
John Paul Tellkamp - Rockwall TX, US
Satyendra Singh Chauhan - Murphy TX, US

International Classification:

H01L 43/14
H01L 43/06
G01R 33/07
G01R 15/20
H01L 23/495

Abstract:

A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including ≥1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to ≥1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

US Patent:

20190355652, Nov 21, 2019

Filed:

Nov 30, 2018

Appl. No.:

16/206640

Inventors:

- Dallas TX, US
Bo-Hsun PAN - Taoyuan City, TW
Yuh-Harng CHIEN - New Taipei City, TW
Fu-Hua YU - New Taipei City, TW
Steven Alfred KUMMERL - Carrollton TX, US
Jie CHEN - Plano TX, US
Rajen M. MURUGAN - Dallas TX, US

International Classification:

H01L 23/495
H01L 21/56
H01L 21/48
H01L 23/31

Abstract:

In an example, an apparatus comprises a lead frame that includes a first row of leads, a first pad coupled to the first row of leads, and a second row of leads parallel to the first row of leads. The lead frame also includes a second pad coupled to the second row of leads. The first and second pads are separated by a gap, and each of the first and second pads has a substantially uniform thickness. The apparatus also includes a device coupled to the first and second pads. The first and second pads are exposed to an exterior of the apparatus.

US Patent:

20180301428, Oct 18, 2018

Filed:

Apr 10, 2018

Appl. No.:

15/949746

Inventors:

Rajen Manicon Murugan - Garland TX, US
Minhong Mi - Newton Center MA, US
Gary Paul Morrison - Garland TX, US
Jie Chen - Denton TX, US
Kenneth Robert Rhyner - Roclwall TX, US
Stanley Craig Beddingfield - Austin TX, US
Chittranjan Mohan Gupta - Richardson TX, US
Django Earl Trombley - Dallas TX, US

International Classification:

H01L 23/66
H01L 23/00
H01Q 1/32
H01L 23/498
H05K 1/02
H05K 1/18
H01Q 1/22
H01Q 23/00

Abstract:

A millimeter wave integrated circuit (IC) chip. The IC chip comprises an IC die and a wire bond ball grid array package encapsulating the IC die. The wire bond ball grid array package comprises a solder ball array, a millimeter wave transmit channel, and a millimeter wave receive channel, wherein each millimeter wave transmit and receive channel electrically couples the IC die to a signal ball of the solder ball array and is configured to resonate at an operating frequency band of the millimeter wave IC chip.