Jie Chen

US Patent:

6653442, Nov 25, 2003

Filed:

Aug 30, 1999

Appl. No.:

09/385328

Inventors:

Conway C. Chang - San Francisco CA
Chee L. Gu - Saratoga CA
Jie Chen - Belmont CA
Deborah A. Steinberg - Saratoga CA
Robert I. Lehrer - Santa Monica CA
Sylvia S. L. Harwig - Woodland Hills CA
Vladimir N. Kokryakov - St. Petersburg, RU

Assignee:

IntraBiotics Pharmaceuticals, Inc. - Mountain View CA

International Classification:

A61K 3804

US Classification:

530324, 530325, 435 691, 4352523, 4353201, 536 231, 514 12, 514 13, 424 49, 424401

Abstract:

Peptide-based compounds containing four invariant cysteine residues which have been optionally oxidized to contain two intramolecular disulfide bonds, or modified forms where the cysteines are replaced are useful as preservatives and in preventing, treating, or ameliorating viral or microbial infection in animals and plants, and in inactivating endotoxin.

US Patent:

7026695, Apr 11, 2006

Filed:

Nov 19, 2003

Appl. No.:

10/718482

Inventors:

Xiao Yang - Sunnyvale CA, US
Shoucheng Zhang - Stanford CA, US
Dongmin Chen - Sunnyvale CA, US
Jie Chen - Saratoga CA, US

Assignee:

Miradia Inc. - Sunnyvale CA

International Classification:

H01L 27/14

US Classification:

257414, 257515, 438 52

Abstract:

An electro-mechanical system, the system comprising a first surface with an electrically activated electrode coupled to the first surface and to an electrical source to receive a first signal. The system further comprising a moveable structure suspended at a first height over the first surface, the moveable structure being attracted toward the electrode based upon the first signal, and the moveable structure being attracted toward the first surface through an interaction with one or more parasitic forces. The systems also provides a landing post coupled to the moveable structure, the landing post being adapted to contact the base of the landing post against the first surface when the electrically activated electrode receives a predetermined voltage bias associated with the first signal, thereby maintaining an outer portion of the moveable structure free from physical contact with the first surface and reducing a magnitude of one or more parasitic forces.

US Patent:

7358772, Apr 15, 2008

Filed:

Feb 28, 2005

Appl. No.:

11/069921

Inventors:

Jie Chen - Saratoga CA, US
Ting-Yen Chiang - Palo Alto CA, US
Kuang-Yu Chen - Saratoga CA, US
Chen Yu Wang - San Jose CA, US
Joe Froniewski - Palo Alto CA, US

Assignee:

Silego Technology, Inc. - Santa Clara CA

International Classification:

H03K 19/0175

US Classification:

326 83, 326 27

Abstract:

A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

US Patent:

7612580, Nov 3, 2009

Filed:

Feb 15, 2008

Appl. No.:

12/070374

Inventors:

Jie Chen - Saratoga CA, US
Ting-Yen Chiang - Palo Alto CA, US
Kuang-Yu Chen - Saratoga CA, US
Chen Yu Wang - San Jose CA, US
Joe Froniewski - Palo Alto CA, US

Assignee:

Silego Technology, Inc. - Santa Clara CA

International Classification:

H03K 19/0175

US Classification:

326 30, 326 27

Abstract:

A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

US Patent:

7749361, Jul 6, 2010

Filed:

Jun 2, 2006

Appl. No.:

11/445690

Inventors:

Jie Chen - Saratoga CA, US
Peijun Ding - Saratoga CA, US
Suraj Rengarajan - San Jose CA, US
Ling Chen - Sunnyvale CA, US
Tram Vo - Milpitas CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

C23C 14/34

US Classification:

20419217, 20429812, 438687

Abstract:

A method of sputtering a copper seed layer and the target used therewith. The copper included in the sputtering target includes a first dopant reactive with copper and a second dopant unreactive with copper. Examples of the first dopant include Ti, Mg, and Al. Examples of the second dopant include Pd, Sn, In, Ir, and Ag. The amount of the first dopant may be determined by testing stress migration and that of the second dopant by testing electromigration.

US Patent:

8138785, Mar 20, 2012

Filed:

Sep 18, 2009

Appl. No.:

12/586288

Inventors:

Jie Chen - Saratoga CA, US
Ting-Yen Chiang - Palo Alto CA, US
Kuang-Yu Chen - Saratoga CA, US
Chen Yu Wang - San Jose CA, US
Joe Froniewski - Palo Alto CA, US

Assignee:

Silego Technology, Inc. - Santa Clara CA

International Classification:

H03K 19/0175

US Classification:

326 30, 326 27

Abstract:

A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

US Patent:

8306256, Nov 6, 2012

Filed:

Sep 16, 2010

Appl. No.:

12/884137

Inventors:

Daniel Gregory Muriello - Palo Alto CA, US
Stephen Charles Heise - Los Altos CA, US
Jie Chen - Sunnyvale CA, US

Assignee:

Facebook, Inc. - Menlo Park CA

International Classification:

G06K 9/00

US Classification:

382100

Abstract:

Users of an online system are authenticated based on signatures of cameras that were used to capture images uploaded to the online system. Users of an online system upload photos taken from their cameras. The online system extracts characteristic information about the camera that captured the photos. This information includes a mapping of faulty pixels, metadata included with the photos, a naming convention, and the like. The online system stores an association between the user and the camera. This association is used for authentication of the user. For authentication, the user is asked to upload new photos taken from the camera that the user used previously. The information extracted from the newly uploaded photos is matched against stored information of cameras used previously by the user. The user is successfully authenticated if the camera used for the newly uploaded photos matches a previously stored camera.

US Patent:

8326723, Dec 4, 2012

Filed:

Aug 25, 2009

Appl. No.:

12/546807

Inventors:

Agus Sudjianto - Matthews NC, US
Michael Chorba - Charlotte NC, US
Daniel Hudson - Charlotte NC, US
Sandi Setiawan - Charlotte NC, US
Jocelyn Sikora - Charlotte NC, US
Harsh Singhal - Charlotte NC, US
Kiran Vuppu - Charlotte NC, US
Kaloyan Mihaylov - New York NY, US
Jie Chen - Charlotte NC, US
Timothy J. Breault - Huntersville NC, US
Arun R. Pinto - Charlotte NC, US
Naveen G. Yeri - Charlotte NC, US
Benhong Zhang - Charlotte NC, US
Zhe Zhang - Charlotte NC, US
Tony Nobili - Charlotte NC, US
Aijun Zhang - Ann Arbor MI, US

Assignee:

Bank of America Corporation - Charlotte NC

International Classification:

G06Q 40/00

US Classification:

705 36R, 705 35, 705 38

Abstract:

A data driven and forward looking risk and reward appetite methodology for consumer and small business is described. The methodology includes customer segmentation to create pools of homogeneous assets in terms of revenue and loss characteristics, forward looking simulation to forecast expected values and volatilities of revenue and loss, and risk and reward optimization of the portfolio. One methodology used for modeling revenue and loss is a generalized additive effect decomposition model to fit historical data. Based on the model, a segmentation procedure is performed, which allows for creation of groups of customers with similar revenue and loss characteristics. An estimation procedure for the model is developed and a simulation strategy to forecast and simulate revenue and loss volatility is developed. Efficient frontier curves of risk (e. g. , return volatility) and reward (e. g.