Jie H Zheng

US Patent:

7119356, Oct 10, 2006

Filed:

Mar 18, 2004

Appl. No.:

10/803244

Inventors:

Zhenan Bao - Stanford CA, US
Jie Zheng - Atlanta GA, US
James C. Sturm - Princeton NJ, US
Troy Graves-Abe - Princeton NJ, US

Assignee:

Lucent Technologies Inc. - Murray Hill NJ
Princeton University - Princeton NJ

International Classification:

H01L 29/06

US Classification:

257 9, 257 14, 257288, 257632, 257E29168, 257E23116

Abstract:

The present invention provides an apparatus and a method of fabricating the apparatus. The apparatus comprises a substrate having a planar surface and first and second electrodes located on the planar surface. The first electrode has a top surface and a lateral surface, and the lateral surface has an edge near or in contact with the substrate. An electrode insulating layer is located on the top surface and a self-assembled layer located on the lateral surface. The second electrode is in contact with both the self-assembled layer and the electrode insulating layer.

US Patent:

7569416, Aug 4, 2009

Filed:

Jun 16, 2006

Appl. No.:

11/424655

Inventors:

Zhenan Bao - Stanford CA, US
Jie Zheng - Atlanta GA, US
James C. Sturm - Princeton NJ, US
Troy Graves-Abe - Princeton NJ, US

Assignee:

Alcatel-Lucent USA Inc. - Murray Hill NJ
Office of Technology Licensing & Intl Property - Princeton NJ

International Classification:

H01L 21/00

US Classification:

438 99, 977858, 977891

Abstract:

The present invention provides an apparatus and a method of fabricating the apparatus. The apparatus comprises a substrate having a planar surface and first and second electrodes located on the planar surface. The first electrode has a top surface and a lateral surface, and the lateral surface has an edge near or in contact with the substrate. An electrode insulating layer is located on the top surface and a self-assembled layer located on the lateral surface. The second electrode is in contact with both the self-assembled layer and the electrode insulating layer.

US Patent:

59207876, Jul 6, 1999

Filed:

Jan 15, 1997

Appl. No.:

8/783312

Inventors:

Jake Haskell - Palo Alto CA
Olivier Laparra - San Jose CA
Jie Zheng - Palo Alto CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01L 2176

US Classification:

438425

Abstract:

A semiconductor device isolating structure and method for forming such a structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall extending to the bottom surface of the trench, and a second sidewall extending to the bottom surface of the trench. Furthermore, the trench of the present invention also has a first field oxide region formed proximate to the interface of the first sidewall and the top surface of the semiconductor substrate, and a second field oxide region formed proximate to the interface of the second sidewall and the top surface of the semiconductor substrate. As a result, the semiconductor substrate has a first rounded corner formed at the intersection of the top surface of semiconductor substrate and the first sidewall, and a second rounded corner formed at the intersection of the top surface of the semiconductor substrate and the second sidewall. In so doing, the present invention eliminates the sharp upper corners found in conventional trenches formed using prior art shallow trench isolation methods.

US Patent:

58829822, Mar 16, 1999

Filed:

Jan 16, 1997

Appl. No.:

8/786365

Inventors:

Jie Zheng - Palo Alto CA
Calvin Todd Gabriel - Cupertino CA
Suzanne Monsees - Campbell CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01L 2176

US Classification:

438424

Abstract:

A shallow trench isolation structure and method for forming such structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall sloping inwardly towards the center of a substantially planar bottom surface, and a second sidewall sloping inwardly towards the center of the substantially planar bottom surface. Additionally, a cross section of the trench has a first rounded bottom trench corner at an interface of the first sidewall and the substantially planar bottom surface, and a second rounded bottom trench corner at an interface of the second sidewall and the substantially planar bottom surface. Furthermore, the trench of the present invention has a first rounded upper trench corner at the interface of the first sidewall and the top surface of the semiconductor substrate, and a second rounded upper trench corner at the interface of the second sidewall and the top surface of the semiconductor substrate. Thus, the trench of the present invention does not have micro-trenches formed into the bottom surface thereof Additionally, the present invention does not have the sharp upper and bottom comers found in conventional trenches formed using a shallow trench isolation method.

US Patent:

61071587, Aug 22, 2000

Filed:

Mar 25, 1998

Appl. No.:

9/047959

Inventors:

Jie Zheng - Palo Alto CA
Calvin Todd Gabriel - Cupertino CA
Suzanne Monsees - Campbell CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01L 21762
H01L 21306

US Classification:

438424

Abstract:

A shallow trench isolation structure and method for forming such structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall sloping inwardly towards the center of a substantially planar bottom surface, and a second sidewall sloping inwardly towards the center of the substantially planar bottom surface. Additionally, a cross section of the trench has a first rounded bottom trench corner at an interface of the first sidewall and the substantially planar bottom surface, and a second rounded bottom trench corner at an interface of the second sidewall and the substantially planar bottom surface. Furthermore, the trench of the present invention has a first rounded upper trench corner at the interface of the first sidewall and the top surface of the semiconductor substrate, and a second rounded upper trench corner at the interface of the second sidewall and the top surface of the semiconductor substrate. Thus, the trench of the present invention does not have micro-trenches formed into the bottom surface thereof.

US Patent:

57535612, May 19, 1998

Filed:

Sep 30, 1996

Appl. No.:

8/723903

Inventors:

Henry C. Lee - San Francisco CA
Calvin T. Gabriel - Cupertino CA
Jie Zheng - Palo Alto CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01L 2176

US Classification:

438424

Abstract:

Disclosed is a method for making a shallow trench structure in a semiconductor substrate. The method includes: (a) forming a mask over a semiconductor substrate, the mask being provided with an aperture extending therethrough which exposes a region of the semiconductor substrate, the aperture having substantially vertical sidewalls; (b) depositing a blanket of silicon over the mask and within the aperture; (c) anisotropically etching the deposited silicon to form temporary spacers having curved profiles at the sidewalls of the aperture, the temporary spacers transferring the curved profiles to a mouth of a shallow trench being etched at the region of the semiconductor substrate as the temporary spacers are etched away; (d) whereby a shallow trench structure is formed where the mouth has a curved profile.

US Patent:

59397659, Aug 17, 1999

Filed:

Nov 24, 1997

Appl. No.:

8/977645

Inventors:

Jie Zheng - Palo Alto CA
Calvin Todd Gabriel - Cupertino CA
Suzanne Monsees - Campbell CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H01L 2900

US Classification:

257510

Abstract:

A shallow trench isolation structure and method for forming such structure. In one embodiment, the semiconductor device isolating structure of the present invention includes a trench formed into a semiconductor substrate. A cross-section of the trench has a first sidewall sloping inwardly towards the center of a substantially planar bottom surface, and a second sidewall sloping inwardly towards the center of the substantially planar bottom surface. Additionally, a cross section of the trench has a first rounded bottom trench corner at an interface of the first sidewall and the substantially planar bottom surface, and a second rounded bottom trench corner at an interface of the second sidewall and the substantially planar bottom surface. Furthermore, the trench of the present invention has a first rounded upper trench corner at the interface of the first sidewall and the top surface of the semiconductor substrate, and a second rounded upper trench corner at the interface of the second sidewall and the top surface of the semiconductor substrate. Thus, the trench of the present invention does not have micro-trenches formed into the bottom surface thereof.