Jim Pay Lin

US Patent:

6775756, Aug 10, 2004

Filed:

Oct 11, 1999

Appl. No.:

09/416196

Inventors:

Shalesh Thusoo - Milpitas CA
Niteen Patkar - Sunnyvale CA
Jim Lin - Sunnyvale CA

Assignee:

ATI International Srl - Barbados

International Classification:

G06F 1200

US Classification:

711169, 711140, 711215, 711214, 712219

Abstract:

A method and apparatus for out-of-order memory processing within an in-order processing device includes processing that allows a plurality of memory transactions to be processed in a pipeline manner until a dependency arises between two or more memory transactions. Such processing includes, for each of the plurality of memory transactions, determining whether data associated with the transaction is stored in local cache. If the data is stored in local cache, it is written into a data register in a next pipeline interval. The processing continues by storing the memory transaction in a miss buffer when the data associated with the memory transaction is not stored in the local cache. The processing continues by writing the associated data for the memory transaction identified in the missed buffer into the data register when the data is received without regard to the pipeline manner.

US Patent:

7826450, Nov 2, 2010

Filed:

Apr 25, 2005

Appl. No.:

11/114734

Inventors:

Jim Lin - Sunnyvale CA, US
Vijayasimha Kadamby - Fremont CA, US

Assignee:

Infineon Technologies AG - Neubiberg

International Classification:

H04L 12/28

US Classification:

370390, 370432

Abstract:

A method and system for routing a multicast packet through a unicast packet switch network of devices. A virtual destination group, which includes destination devices of the multicast packet, is defined, and then the virtual destination group is mapped to an unused unicast destination encoding in routing tables of the devices. The multicast packet is then routed from a source device to the destination devices using the routing tables.

US Patent:

20080141279, Jun 12, 2008

Filed:

Oct 9, 2007

Appl. No.:

11/973895

Inventors:

Peter Mattson - Sunnyvale CA, US
Timothy J. Southgate - Woodside CA, US
Brucek Khailany - San Francisco CA, US
Mark Rygh - Union City CA, US
Jim Jian Lin - Saratoga CA, US
Raghunath Rao - Austin TX, US
Kenneth Hesky - Sunnyvale CA, US
Udo Uebel - San Francisco CA, US

International Classification:

G06F 12/02
G06F 13/00
G06F 1/10
G06F 12/00
G06F 9/46

US Classification:

719313, 711154, 713600, 711100, 718102, 711E12001, 711E12002

Abstract:

Within a data processing system, a user-entered data declaration within a program source file is inspected to determine whether a first qualifier is provided with or omitted from the user-entered data declaration. If the first qualifier is provided, an unreserved data storage location disposed within a data-processing integrated-circuit (IC) device is identified and allocated for storage of data associated with the user-entered data declaration.

US Patent:

20130345892, Dec 26, 2013

Filed:

Jun 21, 2012

Appl. No.:

13/529202

Inventors:

Jim J. Lin - Saratoga CA, US
Kiran B. Kattel - San Francisco CA, US

International Classification:

G05D 23/00

US Classification:

700299

Abstract:

Various embodiments of a thermal control methodology and apparatus are disclosed. In one embodiment, an integrated circuit includes one or more thermal sensors, comparison circuitry, and control circuitry. The comparison circuitry is configured to receive temperature readings from the one or more thermal sensors. The control circuitry is configured to reduce a performance level of one or more controlled subsystems responsive to the comparison circuitry determining that at least one temperature reading from the one or more thermal sensors exceeds one of one or more threshold values. A software-based thermal control mechanism may also execute concurrently with the apparatus.

US Patent:

20150149673, May 28, 2015

Filed:

Nov 25, 2013

Appl. No.:

14/089237

Inventors:

- Cupertino CA, US
Gurjeet S. Saund - Saratoga CA, US
Jim J. Lin - Saratoga CA, US
Timothy R. Paaske - Cupertino CA, US
Ben D. Jarrett - Austin TX, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G06F 13/40
G06F 13/362

US Classification:

710110

Abstract:

Embodiments of a bridge unit and system are disclosed that may allow for processing fence commands send to multiple bridge units. Each bridge unit may process a respective portion of a plurality of transactions generated by a master unit. The master unit may be configured to send a fence command to each bridge unit, which may stall the processing of the command. Each bridge unit may be configured to determine if all transactions included in its respective portion of the plurality of transactions has completed. Once each bridge unit has determined that all other bridge units have received the fence command and that all other bridge units have completed their respective portions of the plurality of transactions that were received prior to receiving the fence command, all bridge units may execute the fence command.