Shalesh Thusoo - Milpitas CA Niteen Patkar - Sunnyvale CA Jim Lin - Sunnyvale CA
Assignee:
ATI International Srl - Barbados
International Classification:
G06F 1200
US Classification:
711169, 711140, 711215, 711214, 712219
Abstract:
A method and apparatus for out-of-order memory processing within an in-order processing device includes processing that allows a plurality of memory transactions to be processed in a pipeline manner until a dependency arises between two or more memory transactions. Such processing includes, for each of the plurality of memory transactions, determining whether data associated with the transaction is stored in local cache. If the data is stored in local cache, it is written into a data register in a next pipeline interval. The processing continues by storing the memory transaction in a miss buffer when the data associated with the memory transaction is not stored in the local cache. The processing continues by writing the associated data for the memory transaction identified in the missed buffer into the data register when the data is received without regard to the pipeline manner.
Multicast/Broadcast Extension To A Point-To-Point Unicast-Only Packet Switch System
Jim Lin - Sunnyvale CA, US Vijayasimha Kadamby - Fremont CA, US
Assignee:
Infineon Technologies AG - Neubiberg
International Classification:
H04L 12/28
US Classification:
370390, 370432
Abstract:
A method and system for routing a multicast packet through a unicast packet switch network of devices. A virtual destination group, which includes destination devices of the multicast packet, is defined, and then the virtual destination group is mapped to an unused unicast destination encoding in routing tables of the devices. The multicast packet is then routed from a source device to the destination devices using the routing tables.
Data Exchange And Communication Between Execution Units In A Parallel Processor
Brucek Khailany - San Francisco CA, US William James Dally - Stanford CA, US Ujval J. Kapasi - San Jose CA, US Jim Jian Lin - Saratoga CA, US
Assignee:
Calos Fund Limited Liability Company - Dover DE
International Classification:
G06F 9/44 G06F 15/76
US Classification:
712225, 712 33
Abstract:
A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval. Each execution lane within the set of the execution lanes is signaled to indicate that the execution lane may send data to the one or others of the execution lanes.
Data Exchange And Communication Between Execution Units In A Parallel Processor
Brucek Khailany - San Francisco CA, US William James Dally - Stanford CA, US Ujval J. Kapasi - San Jose CA, US Jim Jian Lin - Saratoga CA, US
Assignee:
Calos Fund Limited Liability Company - Dover DE
International Classification:
G06F 9/00
US Classification:
712225
Abstract:
Disclosed are methods and systems for dynamically determining data-transfer paths. The data-transfer paths are dynamically determined in response to an instruction that facilitates data transfer among execution lanes in an integrated-circuit processing device operable to execute operations in parallel. In addition, embodiments include an integrated-circuit processing device operable to execute operations in parallel, including the capability of providing confirmation information to potential source lanes, the confirmation information indicating whether the potential source lanes may send data to requested destination lanes during a data-transfer interval.
Brucek Khailany - San Francisco CA, US William James Dally - Stanford CA, US Ujval J. Kapasi - San Jose CA, US Jim Jian Lin - Saratoga CA, US Raghunath Rao - Austin TX, US DeForest Tovey - Los Gatos CA, US Mark Rygh - Union City CA, US Jung-Ho Ahn - Palo Alto CA, US
International Classification:
G06F 9/30 G06F 9/302
US Classification:
712205, 712225, 712221, 712E09016, 712E09017
Abstract:
A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of the execution lanes that may send data to one or more others of the execution lanes during a first interval. Each execution lane within the set of the execution lanes is signaled to indicate that the execution lane may send data to the one or others of the execution lanes.
Software Development For Parallel Processing Systems
Peter Mattson - Sunnyvale CA, US Timothy J. Southgate - Woodside CA, US Brucek Khailany - San Francisco CA, US Mark Rygh - Union City CA, US Jim Jian Lin - Saratoga CA, US Raghunath Rao - Austin TX, US Kenneth Hesky - Sunnyvale CA, US Udo Uebel - San Francisco CA, US
Within a data processing system, a user-entered data declaration within a program source file is inspected to determine whether a first qualifier is provided with or omitted from the user-entered data declaration. If the first qualifier is provided, an unreserved data storage location disposed within a data-processing integrated-circuit (IC) device is identified and allocated for storage of data associated with the user-entered data declaration.
Tracing Command Execution In A Parallel Processing System
Brucek Khailany - San Francisco CA, US Mark Rygh - Union City CA, US Jim Jian Lin - Saratoga CA, US Udo Uebel - San Francisco CA, US
International Classification:
G06F 9/30
US Classification:
712227, 712E09016
Abstract:
Tracing command execution in a data processing system having a host processor and a co-processor. The host processor maintains a record of a plurality of commands for the co-processor, storing each of the plurality of commands is stored in a command queue. Hardware trace logic is provided to store one or more events based, at least in part, on transfer of the plurality of commands to a small memory. Software is executed to store the one or more events to a main memory, wherein the one or more events are aggregated into a single memory trace within the main memory.
Isbn (Books And Publications)
Magic: The Gathering The Pocket Players' Guidefor Magic The Gathering
975 Sereno Dr, Vallejo, CA 94589 7076511000 (Phone)
Certifications:
Anesthesiology, 1998
Awards:
Healthgrades Honor Roll
Languages:
English Chinese, Min Nan
Education:
Medical School University Of Chicago/The Pritzker School Of Medicine Graduated: 1991 Medical School University Hosps Cleveland Graduated: 1992 Medical School Oreg Health Scis University Hospital Graduated: 1994 Medical School University Chicago Hosps Graduated: 1997 Medical School University Hosps Cleveland Graduated: 1993 Medical School University Chicago Hosps Graduated: 1998
University of Chicago, Pritzker School of Medicine - Doctor of Medicine Bernard Mitchell Hospital-University of Chicago Hospitals - Fellowship - Neuroanesthesiology Bernard Mitchell Hospital-University of Chicago Hospitals - Residency - Anesthesiology OHSU Hospitals & Clinics - Residency - Internal Medicine University Hospitals - Case Medical Center - Residency - Internal Medicine
Board certifications:
American Board of Anesthesiology Certification in Anesthesiology
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Jim Lin
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Seely Place Elementary School Scarsdale NY 1974-1976, Monroe Elementary School Hinsdale IL 1976-1977, Hinsdale Junior High School Hinsdale IL 1977-1979