Jin Wang

US Patent:

6715040, Mar 30, 2004

Filed:

Jan 7, 2002

Appl. No.:

10/041932

Inventors:

Jin Chin Wang - Union City CA
Maciek P. Kozyrczak - Bellevue WA

Assignee:

NEC Electronics, Inc. - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711133, 711141, 711159

Abstract:

Described is a data processing system including a processor, a plurality of caches, and main memory, the secondary caches being implemented as being non-inclusive, i. e. , the lower order caches not storing a superset of the data stored in the next higher order cache. The non-inclusive cache structure provides increased flexibility in the storage of data. The operation of a write request operation when the target data line is not found in the primary cache. By using the dirty bit associated with each data line, the interaction between the processor and the primary cache can be reduced. By using the invalidity bit associated with each data line, the interaction between the processor and the primary cache can be reduced.

US Patent:

6931494, Aug 16, 2005

Filed:

Nov 14, 2002

Appl. No.:

10/294415

Inventors:

Kimming So - Palo Alto CA, US
Jin Chin Wang - Union City CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F012/00

US Classification:

711137, 711126

Abstract:

Systems and methods that provide directional prefetching are provided. In one embodiment, a method may include one or more of the following: storing a first block and a second block in a prefetch buffer; associating a first block access with a backward prefetch scheme; associating a second block access with a forward prefetch scheme; and, if the first block is accessed before the second block, then performing a backward prefetch with respect to the first block.

US Patent:

7167954, Jan 23, 2007

Filed:

Nov 14, 2002

Appl. No.:

10/294091

Inventors:

Kimming So - Palo Alto CA, US
Jin Chin Wang - Union City CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 12/00

US Classification:

711137, 711132

Abstract:

Systems and methods that cache are provided. In one example, a system may include a spatial cache system coupled to a processing unit and to a memory. The spatial cache system may be adapted to reduce the memory latency of the processing unit. The spatial cache system may be adapted to store prefetched blocks, each stored prefetched block including a plurality of cache lines. If a cache line requested by the processing unit resides in one of the stored prefetched blocks and does not reside in the processing unit, then the spatial cache system may be adapted to provide the processing unit with the requested cache line.

US Patent:

7515692, Apr 7, 2009

Filed:

Nov 29, 2005

Appl. No.:

11/288603

Inventors:

Jin Wang - Walnut Creek CA, US
Ganeshan Krishnamurthi - Danville CA, US
Raghvendra Savoor - Walnut Creek CA, US

Assignee:

SBC Knowledge Ventures, L.P. - Reno NV

International Classification:

H04M 1/24
H04M 3/08
H04M 3/22

US Classification:

379 2701, 379 104, 379 24, 37939901

Abstract:

A method for qualifying a telephone line for very-high-bit-rate digital subscriber line (“VDSL”) service is disclosed. Generally, a telephone line for VDSL service is prequalified based on a length of the telephone line. A VDSL rate of the telephone line is measured and it is determined whether to qualify as VDSL data qualified based on the measured VDSL rate and a VDSL rate threshold. A VDSL video quality of the telephone line is measured and it is determined whether to qualify the telephone line as VDSL video qualified based on the measured VDSL video quality. Finally, a network database is updated with the determined VDSL data and video qualifications of the telephone line.

US Patent:

7601563, Oct 13, 2009

Filed:

Jan 18, 2007

Appl. No.:

11/624615

Inventors:

Ben Wei Chen - Fremont CA, US
Jin S. Wang - Torrance CA, US
David Hong-Dien Chen - Irvine CA, US

Assignee:

Kingston Technology Corporation - Fountain Valley CA

International Classification:

H01L 21/50
H01L 21/48
H01L 21/44
H01L 23/02
H01L 23/34
H01L 29/68

US Classification:

438126, 438127, 438124, 438106, 257678, 257679, 257723, 257724, 257E2917

Abstract:

A shape-molding structure of a memory card comprises a circuit substrate, at least one chip, and an encapsulant covering. The upper and lower surfaces of the circuit substrate have a circuit layer and a plurality of electric contacts, respectively. The chip is located on the upper surface of the circuit substrate and electrically connected with the circuit layer. The encapsulant covering is formed by using a mold to press encapsulant entering at least one encapsulant inlet provided on at least one side surface of the circuit substrate. The encapsulant covering encapsulates all the above components with only the electric contacts exposed. A trace mark of the encapsulant inlet remaining on the encapsulant covering is then cut to obtain a shape-molding structure of memory card with an smooth and intact outer appearance.

US Patent:

7606145, Oct 20, 2009

Filed:

Nov 29, 2005

Appl. No.:

11/288927

Inventors:

Jin Wang - Walnut Creek CA, US
Canhui Ou - Danville CA, US
Richard Dennis Hart - Concord CA, US
Raghvendra Savoor - Walnut Creek CA, US
Stephen A. Sposato - Lafayette CA, US

Assignee:

SBC Knowledge Ventures, L.P. - Reno NV

International Classification:

H04L 12/26

US Classification:

370228, 34082501

Abstract:

A dual-mode broadband modem operative to operate in a service mode and a surveillance mode is disclosed. Generally, the dual-mode broadband modem comprises a primary communication device; a secondary communication device; a central processing unit in communication with the primary and secondary communication devices; and a memory unit in communication with the central processing unit. In the service mode, the primary communication device communicates with a broadband service provider and the central processing unit stores historical information regarding performance of the primary communication device in the memory unit. If an interruption in broadband service is detected, or the performance of the primary communication device falls below a predetermined threshold, the dual-mode broadband modem switches to surveillance mode and the secondary communication device is activated. The secondary communication device communicates with the broadband service provider to send at least a portion of the historical information regarding performance of the primary communication device to the broadband service provider for processing to determine a source of the interruption in broadband service or a source of the decreased performance of the primary communication device.

US Patent:

7627720, Dec 1, 2009

Filed:

Apr 8, 2005

Appl. No.:

11/101768

Inventors:

Kimming So - Palo Alto CA, US
Jin Chin Wang - Union City CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

711137

Abstract:

Systems and methods that provide directional prefetching are provided. In one embodiment, a method may include one or more of the following: storing a first block and a second block in a prefetch buffer; associating a first block access with a backward prefetch scheme; associating a second block access with a forward prefetch scheme; and, if the first block is accessed before the second block, then performing a backward prefetch with respect to the first block.

US Patent:

7639022, Dec 29, 2009

Filed:

Aug 2, 2006

Appl. No.:

11/461972

Inventors:

Jin Wang - Union City CA, US

Assignee:

AT&T Intellectual Property I, L.P. - Reno NV

International Classification:

G01R 31/00

US Classification:

324533, 324534

Abstract:

A method and apparatus for measuring data rates is disclosed. An apparatus that incorporates teachings of the present disclosure may include, for example, a diagnostic system having a Time Domain Reflectometer (TDR) element that submits a signal over a cable and determines from its reflection in the cable a length of the cable and a length of a bridged tap, and a diagnostic element that determines downstream and upstream bit rates for the cable according to the length of the cable and the length of the bridged tap. Additional embodiments are disclosed.