Jin Zhang

US Patent:

7924054, Apr 12, 2011

Filed:

Feb 16, 2010

Appl. No.:

12/706227

Inventors:

James Doubler - Wheaton IL, US
Michael Hammer - Westchester IL, US
Jin Zhang - Lake Zurich IL, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19/177

US Classification:

326 41, 326 93

Abstract:

A programmable logic device (PLD), is provided that includes: a plurality of SERDES channels; a programmable logic fabric configured to implement an interface for a standardized cellular base station system; wherein the interface receives data words from the SERDES channels and transmits data words to the SERDES channels, and wherein a standard corresponding to the standardized base station system restricts a latency with regard to flow of the data words through the interface, the data words being arranged into frames; and a timing measurement circuit configured to measure a delay between a detection of a first timing point in the frames at first location in the PLD with respect to the interface and a detection of a second timing point in the frames at a second location in the PLD with respect to the interface.

US Patent:

8138790, Mar 20, 2012

Filed:

Apr 11, 2011

Appl. No.:

13/083889

Inventors:

James Doubler - Wheaton IL, US
Michael Hammer - Westchester IL, US
Jin Zhang - Lake Zurich IL, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19/177

US Classification:

326 41, 326 93

Abstract:

In one embodiment, a programmable logic device (PLD) includes a programmable fabric and hard logic coupled to the programmable fabric. The hard logic includes a timing measurement circuit adapted to measure latency of a data path between first and second points in the programmable logic device, such as the latency of a data path through a link interface configured within the programmable fabric.

US Patent:

8165164, Apr 24, 2012

Filed:

Jun 30, 2009

Appl. No.:

12/494822

Inventors:

Michael Hammer - Westchester IL, US
David Pierce - Wheaton IL, US
Jin Zhang - Lake Zurich IL, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H04J 3/24

US Classification:

370474, 370535

Abstract:

A mapping circuit is provided for mapping first data words into frames of second data words, wherein the first and second data words are of different length. In addition, a de-mapping circuit is provided for de-mapping the frames of second data words into the first data words. The mapping and de-mapping is responsive to address signals that may be stored in a memory such that a desired mapping or de-mapping corresponds to a particular programming of the memory. In this fashion, the mapping and de-mapping is in-system reconfigurable.

US Patent:

8495264, Jul 23, 2013

Filed:

Jul 8, 2011

Appl. No.:

13/178536

Inventors:

Michael Hammer - Westchester IL, US
Jin Zhang - Lake Zurich IL, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G06F 13/12
H04L 7/00

US Classification:

710 71, 375354

Abstract:

Parallel data generated by demultiplexing received serial data such as in a Serial RapidIO (SRIO) data stream can become misaligned as a result of, e. g. , clock tolerance compensation (CTC) processing at the receiver. In one embodiment of the invention, the misaligned parallel data is properly aligned based on a mapping from each of a finite number of possible previous alignment conditions (e. g. , words A-D) to a corresponding finite number of possible subsequent alignment conditions (e. g. , words B-G). The change from a previous alignment condition to a different subsequent alignment condition is recognized by determining the location of start-of-packet (SOP) or start-of-control-symbol (SOC) data in the parallel data stream.