Jing Lin

age ~51

from New York, NY

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Also known as:

Lin J Ing

Phone and address:: 15 E 40Th St RM 600, New York, NY 10016
6465094592

Connected to:

Jing Lin Phones & Addresses

15 E 40Th St RM 600, New York, NY 10016 • 6465094592
Berkeley, CA
Eugene, OR

Lawyers & Attorneys

Jing Jing Lin

Jing Lin - Lawyer

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Address:

Skadden Arps Slate Meagher & Flom
37404748xx (Office)

Licenses:

New York - Currently registered 2007

Education:

Cornell Law School

Resumes

Jing Lin Brooklyn, NY

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Work:

Lucky Chinese Restaurant

Aug 2012 to Present
Cashier The City College of
New York, NY
Jul 2012 to Aug 2012
Reference Office Assistant Panda China Buffet
Walton, FL
Jun 2011 to Aug 2011
Manager World Financial Group
New York, NY
Apr 2009 to Jan 2010
Life Health Insurance Sales Associate Dehai Zhang Law Office
New York, NY
Apr 2009 to Aug 2009
Receptionist High School Honor Society

2007 to 2008
Volunteer High School Honor Society

2005 to 2008 High School Honor Society

2006 to 2007
Volunteer

Education:

Fort Hamilton High School
Jun 2008
Diploma The City College of New York
New York, NY
Bachelor of Arts in Management and Administration/Economics

Jing Lin New York, NY

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Work:

World Financial Group
New York, NY
Jun 2012 to Dec 2012
Associate Deloitte Tax LLP
Jericho, NY
Oct 2010 to Jun 2012
Tax Staff

Education:

UNIVERSITY OF NOTRE DAME
Notre Dame, IN
May 2010
Bachelor of Business Administration in Accounting

Vehicle Records

Jing Lin
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Address:

1350 5 Ave APT 5D, New York, NY 10026
Phone:

2122896829
VIN:

5FNYF4H56CB012054
Make:

HONDA
Model:

PILOT
Year:

2012

Real Estate Brokers

Jing Lin, New York NY Agent

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Work:

Anchor Associates
New York, NY
3477220474 (Phone)

License Records

Jing Lin

License #:

58175 - Expired

Category:

Nursing

Issued Date:

Dec 20, 2000

Effective Date:

Jan 3, 2003

Expiration Date:

Oct 31, 2002

Type:

Registered Nurse

Medicine Doctors

Jing Lin, New York NY

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Specialties:

Neonatal-Perinatal Medicine Specialist
Pediatrician

Address:

1176 Fifth Ave, New York, NY 10029

Education:

Medical School - MD, Wenzhou Medical College
Yuying Children's Hospital (Residency - Pediatrics)
New York University Medical Center (Residency - Pediatrics)
Mount Sinai Hospital (Fellowship - Neonatology)
University of Miami

Languages:

English
Chinese (Mandarin)

Awards and Publications:

Howe TH, Sheu CF, Hinojosa J, Lin J, Holzman IR. Multiple factors related to bottle-feeding performance in preterm infants. Nurs Res 2007; 56: 307-311.
Gibbs K, Lin J, Holzman IR. Necrotizing enterocolitis: the state of the science. Indian J Pediatrics 2007; 74: 67-72.
Peng LY, He ZJ, Chen W, Holzman IR, Lin J. Effects of short chain fatty acid on intestinal barrier function in a Caco-2 cell monolayer model. Pediatr Res 2007; 61: 37-41.
Lin ZL, Yu HM, Lin J, Chen SQ, Liang ZQ, Zhang ZY. Mild hypothermia via selective head cooling as neuroprotective therapy in term neonates with perinatal asphyxia: an experience from a single neonatal intensive care unit. J Perinatol 2006; 26: 180-184.
Lin J, Peng LY, Itzkowitz S, Holzman IR, Babyatsky MW. Short-chain fatty acid induces intestinal mucosal injury in newborn rats and down-regulates intestinal trefoil factor gene expression in vivo and in vitro. J Pediatr Gastr Nutr 2005; 41: 607-611.
Nafday SM, Green RS, Lin J, Oschorn I, Brion L, Holzman IR. Is there an advantage of using pressure support ventilation with volume guarantee in the initial management of premature infants with respiratory distress syndrome? - A pilot study. J Perinatol 2005; 25: 193-197.
Nafday SM, Peng LY, Babyatsky MW. Short chain fatty acids induce colonic mucosal injury in rats with different postnatal ages. Pediatr Res 2005; 57: 201-204.
Yu K, Jiang SF, Lin MF, Wu JB, Lin J. Extraction and purification of biologically active intestinal trefoil factor from human meconium. Lab Invest 2004; 84: 390-392.
Lin J. Too much short chain fatty acids cause neonatal necrotizing enterocolitis. Med Hypotheses 2004; 62: 291-293.
Lin J, Nadroo AM, Chen W, Fan QX, Holzman IR, Babyatsky MW. Ontogeny and prenatal expression of trefoil factor 3/ITF in the human intestine. Early Hum Dev 2003; 71: 103-109.
Chen SQ, Chen JN, Cai XH, Chen GR, Gao Y, Ge RS, Wu HS, Lin ZL, Lin J. Perinatal exposure to di-(2-ethylhexyl) phthalate leads to restricted growth and delayed lung maturation in newborn rats. J Perinat Med 2010; 38: 515-521.
Hu GX, Chen GR, Xu H, Ge RS, Lin J. Activation of the AMP activated protein kinase by short chain fatty acids is the main mechanism underlying the beneficial effect of a high fiber diet on the metabolic syndrome. Medical Hypotheses 2010; 74: 123-126.
Liu XL, Zhou R, Pan QQ, Jia XL, Gao WN, Wu J, Lin J, Chen JF. Genetic inactivation of the adenosine A2A receptor attenuates pathological but not developmental angiogenesis in mouse retina. Invest Ophthalmol Vis Sci 2010; 51: 6625-6632.
Peng LY, Li ZR, Green RS, Holzman IR, Lin J. Butyrate Enhances the Intestinal Barrier by Facilitating Tight Junction Assembly via Activation of AMP Activated Protein Kinase in Caco-2 Cell Monolayers. J Nutr 2009; 139: 1619-25.
Xu Z, Chen Y, Yang M, Li W, Liu Q, Lin J. The epidemiological and clinical characteristics of measles in Wenzhou, China, 2000-2010. . Epidemiology and Infection 2014; 142: 20-27
Bao S, Zhu L, Zhuang Q, Wang L, Xu P, Itoh K, Holzman I, Lin J. Distribution dynamics of recombinant Lactobacillus in the gastrointestinal tract of neonatal rats. . PLOS ONE 2013; 8: e60007.

Board certifications:

American Board of Pediatrics
Neonatal-Perinatal Medicine (Pediatrics)

Jing Lin, New York NY - BM

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Specialties:

Neonatal Medicine

Address:

Mount Sinai Medical Center
1176 5Th Ave Suite 1173, New York, NY 10029
2124279898 (Phone), 2122892733 (Fax)

Mt Sinai Hosp Newborn Medcn
1176 5Th Ave Suite 316, New York, NY 10029
2122415446 (Phone)

Certifications:

Pediatrics, 1997
Perinatal Medicine & Neonatal Medicine, 1999

Awards:

Healthgrades Honor Roll

Languages:

English
Chinese

Education:

Medical School
Wenzhou Med Coll
Medical School
Bellevue Hospital Center
Medical School
Mount Sinai Hospital

Jing Lin

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Specialties:

Neonatal-Perinatal Medicine

Work:

Newborn Medicine AssociatesMount Sinai Hospital Newborn Medicine
1184 5 Ave STE 341, New York, NY 10029
2122415446 (phone), 2125345207 (fax)

Education:

Medical School
Wenzhou Med Coll, Wenzhou, Zhejiang, China
Graduated: 1983

Languages:

English
Spanish

Description:

Dr. Lin graduated from the Wenzhou Med Coll, Wenzhou, Zhejiang, China in 1983. He works in New York, NY and specializes in Neonatal-Perinatal Medicine. Dr. Lin is affiliated with Mount Sinai Medical Center.

Name / Title

Company / Classification

Phones & Addresses

Jing Lin
President

Da Xin Video Store Inc
Whol Durable Goods

4010 Main St, Flushing, NY 11354
7189136375

Jing J. Lin
Principal

Jing Jin Lin Plumbing Co
Plumbing/Heating/Air Cond Contractor

42 Lee Ave, San Francisco, CA 94112
4153342928

Jing Lin
Principal

LIN'S LAUNDROMAT KINGS INC
Coin-Operated Laundry

835 Broadway, Brooklyn, NY 11206
7187822889

Jing Lin
Chairman

Eastern
Repair Services

327 Rte 303, Orangeburg, NY 10962

Jing Lin

Spoil Yourself, LLC
Personal Services-Massage

100 W Broadway, Glendale, CA 91210
5147 Xavier Cmn, Fremont, CA 94555
130 14 St, Oakland, CA 94612
5108930803

Jing Lin

LIN'S RESTAURANT LC

Jing Lin

Jing Lin MD
Pediatrician

1176 5 Ave, New York, NY 10029
2122415446

Jing Lin

EASTERN BUFFET LLC

Us Patents

Method For Automatically Generating Checkers For Finding Functional Defects In A Description Of A Circuit
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US Patent:

6609229, Aug 19, 2003
Filed:

Aug 9, 2000
Appl. No.:

09/635598
Inventors:

Tai An Ly - Fremont CA
Jean-Charles Giomi - Menlo Park CA
Kalyana C. Mulam - San Jose CA
Paul Andrew Wilcox - Palo Alto CA
David Lansing Dill - Redwood City CA
Paul Estrada, II - Los Altos CA
Jing Chyuarn Lin - Sunnyvale CA
Robert Kristianto Mardjuki - Danville CA
Ping Fai Yeung - San Jose CA
Assignee:

O-In Design Automation, Inc. - San Jose CA
International Classification:

G06F 1750
US Classification:

716 4, 703 14, 703 17
Abstract:

A programmed computer generates descriptions of circuits (called âcheckersâ) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuits description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuits description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers.

Method For Automatically Searching For Functional Defects In A Description Of A Circuit
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US Patent:

6885983, Apr 26, 2005
Filed:

May 4, 2001
Appl. No.:

09/849005
Inventors:

Robert Kristianto Mardjuki - Danville CA, US
David Lansing Dill - Redwood City CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Ping Fai Yeung - San Jose CA, US
Paul Il Estrada - Los Alto CA, US
Jean-Charles Giomi - Menlo Park CA, US
Tai An Ly - Fremont CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US
Assignee:

Mentor Graphics Corporation - Wilsonville OR
International Classification:

G06F017/50
US Classification:

703 14, 703 15, 703 16, 716 4
Abstract:

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Method For Automatically Generating Checkers For Finding Functional Defects In A Description Of Circuit
view source
US Patent:

7007249, Feb 28, 2006
Filed:

Jan 20, 2003
Appl. No.:

10/348116
Inventors:

Tai An Ly - Fremont CA, US
Jean-Charles Giomi - Menlo Park CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US
David Lansing Dill - Redwood City CA, US
Paul II Estrada - Los Alto CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Robert Kristianto Mardjuki - Danville CA, US
Ping Fai Yeung - San Jose CA, US
International Classification:

G06F 17/50
US Classification:

716 4, 716 5, 703 13, 703 20, 703 23, 703 28
Abstract:

A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers.

Method For Automatically Searching For Functional Defects In A Description Of A Circuit
view source
US Patent:

7478028, Jan 13, 2009
Filed:

Jan 12, 2005
Appl. No.:

11/035275
Inventors:

Robert Kristianto Mardjuki - Danville CA, US
David Lansing Dill - Redwood City CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Ping Fai Yeung - San Jose CA, US
Paul II Estrada - Los Alto CA, US
Jean-Charles Giomi - Menlo Park CA, US
Tai An Ly - Fremont CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US
International Classification:

G06F 17/50
US Classification:

703 14, 703 15, 703 16, 716 4
Abstract:

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first-controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Vapor Deposition Of Tungsten Materials
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US Patent:

7732327, Jun 8, 2010
Filed:

Sep 26, 2008
Appl. No.:

12/239046
Inventors:

Avgerinos V. Gelatos - Redwood City CA, US
Kai Wu - Palo Alto CA, US
Amit Khandelwal - Santa Clara CA, US
Ross Marshall - Sunnyvale CA, US
Emily Renuart - Santa Clara CA, US
Wing-Cheong Gilbert Lai - Santa Clara CA, US
Jing Lin - Mountain View CA, US
Assignee:

Applied Materials, Inc. - Santa Clara CA
International Classification:

H01L 21/4763
US Classification:

438649, 438683, 427255392, 257E21165
Abstract:

Embodiments of the invention provide an improved process for depositing tungsten-containing materials. The process utilizes soak processes and vapor deposition processes to provide tungsten films having significantly improved surface uniformity while increasing the production level throughput. In one embodiment, a method is provided which includes depositing a tungsten silicide layer on the substrate by exposing the substrate to a continuous flow of a silicon precursor while also exposing the substrate to intermittent pulses of a tungsten precursor. The method further provides that the substrate is exposed to the silicon and tungsten precursors which have a silicon/tungsten precursor flow rate ratio of greater than 1, for example, about 2, about 3, or greater. Subsequently, the method provides depositing a tungsten nitride layer on the tungsten suicide layer, depositing a tungsten nucleation layer on the tungsten nitride layer, and depositing a tungsten bulk layer on the tungsten nucleation layer.

System And User Interface For Machine-Assisted Human Labeling Of Pixels In An Image
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US Patent:

8452086, May 28, 2013
Filed:

Jul 10, 2009
Appl. No.:

12/500928
Inventors:

Eric Saund - San Carlos CA, US
Jing Lin - Saratoga CA, US
Prateek Sarkar - Sunnyvale CA, US
Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA
International Classification:

G06K 9/34
US Classification:

382164, 715810
Abstract:

A user interface and method is embodied on a computer readable medium and executable on a computer. The user interface is a labeler which labels only foreground pixels of an image stored in a computing environment. The labeler operates in a Region mode/state and Brush mode/state, and includes a Tentative mode that permits an assigned label to be changed after pixels have been selected. Groups of pixels may be selected for labeling at once by a point-and-click command, and a pixel may belong to one or more groups of pixels which are stored in memory as image layers. The groups are formed dynamically by user selection actions, and/or through automatic recognition algorithms. Pixels already labeled with certain labels may be locked to not be altered by additional labeling operations. Unassigned pixels may be highlighted to increase the ease at which they are identified in an image. Comparisons between labeled images are undertaken to indicate differences between different groundtruth labeling.

Temperature Controlled Lid Assembly For Tungsten Nitride Deposition
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US Patent:

20080202425, Aug 28, 2008
Filed:

Jan 29, 2008
Appl. No.:

12/021825
Inventors:

Avgerinos V. Gelatos - Redwood City CA, US
Xiaoxiong Yuan - San Jose CA, US
Salvador P. Umotoy - Antioch CA, US
Yu Chang - San Jose CA, US
Emily Renuart - Santa Clara CA, US
Jing Lin - Mountain View CA, US
Wing-Cheong Lai - Santa Clara CA, US
Sang Q. Le - San Jose CA, US
International Classification:

C23C 16/06
US Classification:

118724
Abstract:

Embodiments of the invention provide apparatuses for vapor depositing tungsten-containing materials, such as metallic tungsten and tungsten nitride. In one embodiment, a processing chamber is provided which includes a lid assembly containing a lid plate, a showerhead, a mixing cavity, a distribution cavity, and a resistive heating element contained within the lid plate. In one example, the resistive heating element is configured to provide the lid plate at a temperature within a range from about 120 C. to about 180 C., preferably, from about 140 C. to about 160 C., more preferably, from about 145 C. to about 155 C. The mixing cavity may be in fluid communication with a tungsten precursor source containing tungsten hexafluoride and a nitrogen precursor source containing ammonia. In some embodiments, a single processing chamber may be used to deposit metallic tungsten and tungsten nitride materials by CVD processes.

Process For Tungsten Nitride Deposition By A Temperature Controlled Lid Assembly
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US Patent:

20080206987, Aug 28, 2008
Filed:

Jan 29, 2008
Appl. No.:

12/021798
Inventors:

Avgerinos V. Gelatos - Redwood City CA, US
Xiaoxiong Yuan - San Jose CA, US
Salvador P. Umotoy - Antioch CA, US
Yu Chang - San Jose CA, US
Emily Renuart - Santa Clara CA, US
Jing Lin - Mountain View CA, US
Wing-Cheong Lai - Santa Clara CA, US
Sang Q. Le - San Jose CA, US
International Classification:

H01L 21/44
US Classification:

438654, 257E21476
Abstract:

Embodiments of the invention provide processes for vapor depositing tungsten-containing materials, such as metallic tungsten and tungsten nitride. In one embodiment, a method for forming a tungsten-containing material is provided which includes positioning a substrate within a processing chamber containing a lid plate, heating the lid plate to a temperature within a range from about 120 C. to about 180 C., exposing the substrate to a reducing gas during a pre-nucleation soak process, and depositing a first tungsten nucleation layer on the substrate during a first atomic layer deposition process within the processing chamber. The method further provides depositing a tungsten nitride layer on the first tungsten nucleation layer during a vapor deposition process, depositing a second tungsten nucleation layer on the tungsten nitride layer during a second atomic layer deposition process within the processing chamber, and exposing the substrate to another reducing gas during a post-nucleation soak process.