Jing Lin

US Patent:

6609229, Aug 19, 2003

Filed:

Aug 9, 2000

Appl. No.:

09/635598

Inventors:

Tai An Ly - Fremont CA
Jean-Charles Giomi - Menlo Park CA
Kalyana C. Mulam - San Jose CA
Paul Andrew Wilcox - Palo Alto CA
David Lansing Dill - Redwood City CA
Paul Estrada, II - Los Altos CA
Jing Chyuarn Lin - Sunnyvale CA
Robert Kristianto Mardjuki - Danville CA
Ping Fai Yeung - San Jose CA

Assignee:

O-In Design Automation, Inc. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 4, 703 14, 703 17

Abstract:

A programmed computer generates descriptions of circuits (called âcheckersâ) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuits description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die The circuits description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging detective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers.

US Patent:

6885983, Apr 26, 2005

Filed:

May 4, 2001

Appl. No.:

09/849005

Inventors:

Robert Kristianto Mardjuki - Danville CA, US
David Lansing Dill - Redwood City CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Ping Fai Yeung - San Jose CA, US
Paul Il Estrada - Los Alto CA, US
Jean-Charles Giomi - Menlo Park CA, US
Tai An Ly - Fremont CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US

Assignee:

Mentor Graphics Corporation - Wilsonville OR

International Classification:

G06F017/50

US Classification:

703 14, 703 15, 703 16, 716 4

Abstract:

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

US Patent:

7007249, Feb 28, 2006

Filed:

Jan 20, 2003

Appl. No.:

10/348116

Inventors:

Tai An Ly - Fremont CA, US
Jean-Charles Giomi - Menlo Park CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US
David Lansing Dill - Redwood City CA, US
Paul II Estrada - Los Alto CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Robert Kristianto Mardjuki - Danville CA, US
Ping Fai Yeung - San Jose CA, US

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 703 13, 703 20, 703 23, 703 28

Abstract:

A programmed computer generates descriptions of circuits (called “checkers”) that flag functional defects in a description of a circuit undergoing functional verification. The programmed computer automatically converts the circuit's description into a graph, automatically examines the graph for instances of a predetermined arrangement of nodes and connections, and automatically generates instructions that flag a behavior of a device represented by the instance in conformance with a known defective behavior. The checkers can be used during simulation or emulation of the circuit, or during operation of the circuit in a semiconductor die. The circuit's description can be in Verilog or VHDL and the automatically generated checkers can also be described in Verilog or VHDL. Therefore, the checkers can co-simulate with the circuit, monitoring the simulated operation of the circuit and flagging defective behavior. The programmed computer can automatically determine load conditions of registers in the circuit and automatically generate checkers to flag data loss in the registers.

US Patent:

7478028, Jan 13, 2009

Filed:

Jan 12, 2005

Appl. No.:

11/035275

Inventors:

Robert Kristianto Mardjuki - Danville CA, US
David Lansing Dill - Redwood City CA, US
Jing Chyuarn Lin - Sunnyvale CA, US
Ping Fai Yeung - San Jose CA, US
Paul II Estrada - Los Alto CA, US
Jean-Charles Giomi - Menlo Park CA, US
Tai An Ly - Fremont CA, US
Kalyana C. Mulam - San Jose CA, US
Paul Andrew Wilcox - Palo Alto CA, US

International Classification:

G06F 17/50

US Classification:

703 14, 703 15, 703 16, 716 4

Abstract:

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first-controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

US Patent:

7552409, Jun 23, 2009

Filed:

Jun 7, 2005

Appl. No.:

11/147814

Inventors:

Kayhan Kucukcakar - Sunnyvale CA, US
Jing C. Lin - Cupertino CA, US
Jinan Lou - Cupertino CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716 5, 716 6, 703 16

Abstract:

A method for reaching signoff closure in an ECO (engineering change order) process involves the use of violation context data from the signoff tool as the basis for design layout modifications in an implementation tool. The violation context data includes violation information other than violation location/path information. Because the signoff tool, and more specifically, the signoff algorithm used by that tool is the most accurate model of actual IC behavior, the use of violation context data generated by the signoff tool to implement changes to the design layout will generally produce appropriate and effective results. By accessing this violation context data from the signoff tool, an implementation tool need not rely on its less accurate implementation analysis to determine the optimal design layout modifications for correcting violations detected by the signoff tool.

US Patent:

7732327, Jun 8, 2010

Filed:

Sep 26, 2008

Appl. No.:

12/239046

Inventors:

Avgerinos V. Gelatos - Redwood City CA, US
Kai Wu - Palo Alto CA, US
Amit Khandelwal - Santa Clara CA, US
Ross Marshall - Sunnyvale CA, US
Emily Renuart - Santa Clara CA, US
Wing-Cheong Gilbert Lai - Santa Clara CA, US
Jing Lin - Mountain View CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/4763

US Classification:

438649, 438683, 427255392, 257E21165

Abstract:

Embodiments of the invention provide an improved process for depositing tungsten-containing materials. The process utilizes soak processes and vapor deposition processes to provide tungsten films having significantly improved surface uniformity while increasing the production level throughput. In one embodiment, a method is provided which includes depositing a tungsten silicide layer on the substrate by exposing the substrate to a continuous flow of a silicon precursor while also exposing the substrate to intermittent pulses of a tungsten precursor. The method further provides that the substrate is exposed to the silicon and tungsten precursors which have a silicon/tungsten precursor flow rate ratio of greater than 1, for example, about 2, about 3, or greater. Subsequently, the method provides depositing a tungsten nitride layer on the tungsten suicide layer, depositing a tungsten nucleation layer on the tungsten nitride layer, and depositing a tungsten bulk layer on the tungsten nucleation layer.

US Patent:

8336015, Dec 18, 2012

Filed:

Jan 29, 2010

Appl. No.:

12/697142

Inventors:

Chi-Min Chu - Cupertino CA, US
Jing C. Lin - Cupertino CA, US

Assignee:

Synopsys, Inc. - Mountain View CA

International Classification:

G06F 17/50

US Classification:

716132

Abstract:

A method of improving pre-route and post-route correlation can include performing an initial placement, virtual routing, and lower-effort actual routing for the design. The results of the virtual routing and lower-effort actual routing can be compared to identify nets having miscorrelation. Based on the nets having at least a predetermined miscorrelation, one or more patterns can be defined. At this point, net routing constraints and/or scaling factors can be assigned to nets matching the defined patterns. These net routing constraints and scaling factors can be applied to the nets of the design that match the patterns. Optimized placement and a higher-effort actual routing of the design can be performed using the nets with the applied net routing constraints and scaling factors. An optimized, routed design can be generated as output.

US Patent:

8452086, May 28, 2013

Filed:

Jul 10, 2009

Appl. No.:

12/500928

Inventors:

Eric Saund - San Carlos CA, US
Jing Lin - Saratoga CA, US
Prateek Sarkar - Sunnyvale CA, US

Assignee:

Palo Alto Research Center Incorporated - Palo Alto CA

International Classification:

G06K 9/34

US Classification:

382164, 715810

Abstract:

A user interface and method is embodied on a computer readable medium and executable on a computer. The user interface is a labeler which labels only foreground pixels of an image stored in a computing environment. The labeler operates in a Region mode/state and Brush mode/state, and includes a Tentative mode that permits an assigned label to be changed after pixels have been selected. Groups of pixels may be selected for labeling at once by a point-and-click command, and a pixel may belong to one or more groups of pixels which are stored in memory as image layers. The groups are formed dynamically by user selection actions, and/or through automatic recognition algorithms. Pixels already labeled with certain labels may be locked to not be altered by additional labeling operations. Unassigned pixels may be highlighted to increase the ease at which they are identified in an image. Comparisons between labeled images are undertaken to indicate differences between different groundtruth labeling.