Jipeng Li

US Patent:

7372391, May 13, 2008

Filed:

Feb 21, 2007

Appl. No.:

11/677358

Inventors:

Matthew Courcy - Fremont NH, US
Jipeng Li - Nashua NH, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03M 1/38

US Classification:

341161, 341155

Abstract:

A data conversion stage circuit () for an opamp-shared pipeline analog-to-digital converter (ADC) () includes an over-range detection and recovery circuit including first and second switches (S, S) connected between respective input terminals () and output terminals () of the opamp () and both controlled by a first control signal, and a logic circuit () coupled to receive the first residue value and compare the first residue value to a pair of high and low comparison voltage levels. The logic circuit asserts the first control signal during a first clock phase when the first residue value is either greater than the high comparison voltage level or less than the low comparison voltage level. The high and low comparison voltage levels define a voltage region outside of a reference voltage range of the data conversion stage circuit where the reference voltage range defines in-range voltage values for the data conversion stage circuit.

US Patent:

8031098, Oct 4, 2011

Filed:

Jan 19, 2010

Appl. No.:

12/689874

Inventors:

Christian Ebner - München, DE
Jipeng Li - Windham NH, US
Bernd Schafferer - Gloucester MA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03M 1/72

US Classification:

341146, 341144

Abstract:

In one embodiment, digital-to-analog converter (DAC) circuit includes dual DAC units employing pseudo-return-to-zero DAC operations to reduce inter-symbol interference. Moreover, each DAC unit is implemented using complementary MOS transistors to improve conversion performance. In another embodiment, a DAC calibration scheme performs background calibration of an array of DAC circuits in continuous time using a reference DAC circuit and a spare DAC circuit. Calibration (also referred to as “trimming”) of the DAC circuit using the calibration scheme of the present invention ensures that the DAC operates with high linearity over process variations. In one embodiment, the DAC circuit and the DAC calibration scheme are applied as the feedback DAC in a continuous-time sigma-delta (CT-ΣΔ) analog-to-digital converter to realize high performance and high precision analog-to-digital conversions.

US Patent:

20140078795, Mar 20, 2014

Filed:

Sep 14, 2012

Appl. No.:

13/617548

Inventors:

Jipeng Li - Windham NH, US
Richard E. Schreier - Toronto, CA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H02M 3/18

US Classification:

363 60

Abstract:

A voltage generator may include a plurality of charge pumps, plural sets of delay pipelines and a phase controller. Given M delay pipelines having N stages each, there may be M*N charge pumps each having a triggering input coupled to a respective stage or a respective pipeline. The phase controller may include a plurality of phase control stages interconnecting among the delay pipelines to induce timing offsets among the outputs of the delay stage. In an alternate design, intermediate nodes among the pipeline's delay stages may be coupled to triggering inputs of a sub-set of the charge pumps. The phase controller may have a plurality of phase control stages coupled, respectively, between the intermediate nodes of the delay pipeline and intermediate nodes of the phase control stages may be coupled to triggering inputs of another sub-set of the charge pumps.

US Patent:

7345530, Mar 18, 2008

Filed:

Jun 1, 2006

Appl. No.:

11/421716

Inventors:

Jipeng Li - Nashua NH, US
Matthew Courcy - Fremont NH, US
Gabriele Manganaro - Boxborough MA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03F 1/02

US Classification:

330 9, 330 51

Abstract:

A switched-capacitor amplifier circuit including first and second pairs of sampling capacitors for sampling a pair of input signals includes a voltage regulator coupled to receive a first reference voltage and generate a first regulated output voltage related to the first reference voltage and independent of a first power supply voltage; a clock signal generator generating first and second clock signals referenced to the first power supply voltage and third and fourth clock signals referenced to the first regulated output voltage; and a first set of switches coupling the bottom plates of the sampling capacitors to the amplifier, the first set of switches being controlled by the third and fourth clock signals. The circuit may further include a second set of switches coupling the top plates of the sampling capacitors to the input signals, the second set of switches being controlled by the first and second clock signals.

US Patent:

20150123828, May 7, 2015

Filed:

Nov 6, 2013

Appl. No.:

14/073396

Inventors:

- Hamilton, BM
Jipeng Li - Windham NH, US
Richard E. Schreier - Toronto, CA
Hajime Shibata - Toronto, CA

Assignee:

ANALOG DEVICES TECHNOLOGY - Hamilton

International Classification:

H03M 3/00
H03M 1/18

US Classification:

341143

Abstract:

In one example implementation, the present disclosure provides a loop filter for use in a continuous-time sigma-delta analog-to-digital converter. Specifically, a capacitive feedback digital-to-analog converter path is provided at the input of a first opamp in a series of opamp integrators. The capacitive feedback digital-to-analog converter at the input of the first opamp reduces the signal content at the output of the first opamp, and thereby reduces the output swing of the first opamp. A reduction in output swing provides a more efficient loop filter.