Jochen Titus

US Patent:

20130000702, Jan 3, 2013

Filed:

Jun 30, 2011

Appl. No.:

13/173407

Inventors:

Korhan Demirkan - Santa Clara CA, US
Jochen Titus - Sunnyvale CA, US
Robert Tas - Aromas CA, US

Assignee:

MiaSole - Santa Clara CA

International Classification:

H01L 31/02
H01L 31/18

US Classification:

136252, 438 73, 257E31001

Abstract:

A photovoltaic device including a substrate, a first electrode layer over the substrate and a resistive p-type semiconductor layer over the first electrode layer. The device also includes a p-type absorber layer over the resistive p-type semiconductor layer, an n-type semiconductor layer over the p-type absorber layer and a second electrode layer over the n-type semiconductor layer. Additionally, a resistivity of the resistive p-type semiconductor layer is greater than a resistivity of the p-type absorber layer.

US Patent:

20210111300, Apr 15, 2021

Filed:

Oct 9, 2020

Appl. No.:

17/066786

Inventors:

- Bejing, CN
Ben HICKEY - Redwood City CA, US
Jochen TITUS - San Jose CA, US
Dmitry POPLAVSKYY - San Jose CA, US
Neil MACKIE - Fremont CA, US

International Classification:

H01L 31/18
C23C 14/58
C23C 14/56
C23C 14/06
C23C 14/34

Abstract:

A thin film deposition system and method for forming photovoltaic cells, the system including a first deposition module including a titanium sputtering target and configured to deposit a titanium precursor layer of a diffusion barrier on the substrate, as the substrate moves through the first deposition module; a second deposition module configured to deposit a first electrode onto the diffusion barrier, as the substrate moves through the second deposition module; and a first connection unit configured to nitride at least a portion of the titanium precursor layer of the diffusion barrier, while the substrate moves though the first connection unit from the first deposition module to the second deposition module.

US Patent:

20200194609, Jun 18, 2020

Filed:

Dec 18, 2018

Appl. No.:

16/223945

Inventors:

- Beijing, CN
Geordie Zapalac - Santa Cruz CA, US
Timothy Nagle - Campbell CA, US
Weijie Zhang - San Jose CA, US
Jochen Titus - Sunnyvale CA, US

International Classification:

H01L 31/0749
H01L 31/18
H01L 31/0224
H01L 31/0336
C23C 14/06
C23C 14/34
C23C 14/08

Abstract:

A method of manufacturing a solar cell including depositing a first electrode over a substrate under vacuum, depositing at least one p-type semiconductor absorber layer over the first electrode without breaking the vacuum, where the p-type semiconductor absorber layer comprises a copper indium selenide (CIS) based alloy material, sputter depositing an n-type semiconductor layer over the at least one p-type semiconductor absorber layer to form zinc oxysulfide in the n-type semiconductor layer without breaking the vacuum, and depositing a second electrode over the n-type semiconductor layer without breaking the vacuum.

US Patent:

20200028013, Jan 23, 2020

Filed:

Jul 20, 2018

Appl. No.:

16/041080

Inventors:

- Beijing, CN
Jochen TITUS - San Jose CA, US

International Classification:

H01L 31/05
H01L 31/032
H01L 31/0224
H01L 31/18

Abstract:

A photovoltaic device interconnect contains a first connection region, a second connection region, and an overlap region disposed between the first and second connection regions. The interconnect includes an electrically conductive layer disposed in the first, second, and overlap regions. The conductive layer includes an electrically conductive network of nanowires. A first dielectric layer is disposed on a lower surface of the conductive layer in the first connection region and the overlap region, and a second dielectric layer is disposed on an upper surface of the conductive layer in the second connection region and the overlap region.

US Patent:

20200028014, Jan 23, 2020

Filed:

Jul 20, 2018

Appl. No.:

16/041137

Inventors:

- Beijing, CN
Jochen TITUS - San Jose CA, US

International Classification:

H01L 31/05
H01L 31/032
H01L 31/0224
H01L 31/18

Abstract:

A photovoltaic device interconnect contains a first connection region, a second connection region, and an overlap region disposed between the first and second connection regions. The interconnect includes a first dielectric layer disposed in the first connection region and the overlap region, a second dielectric layer disposed in the second connection region and overlapped with the first dielectric layer in the overlap region, an electrically conductive element including a wire or a metal foil, disposed on an upper surface of the first dielectric layer, and an electrically conductive network of nanowires disposed on a lower surface of the second dielectric layer and electrically connected to the conductive element in the overlap region.

US Patent:

20180337294, Nov 22, 2018

Filed:

Jul 12, 2018

Appl. No.:

16/034131

Inventors:

- BEIJING, CN
Alex Austin - Carmel Valley CA, US
Robert Tas - Aromas CA, US
Neil Mackie - Fremont CA, US
Mats Larsson - Sunnyvale CA, US
Korhan Demirkan - Santa Clara CA, US
Weijie Zhang - San Jose CA, US
Jochen Titus - Sunnyvale CA, US
Robert Zubeck - Los Altos CA, US
Randy Dorn - Santa Clara CA, US
Asit Rairkar - San Jose CA, US
Ron Rulkens - Milpitas CA, US
Ajay Saproo - Los Altos CA, US
Dan Vitkavage - San Jose CA, US

International Classification:

H01L 31/0224
H01L 31/032
H01L 31/0392
H01L 31/0749

Abstract:

A solar cell containing a plurality of CIGS absorber sublayers has a conversion efficiency of at least 13.4 percent and a minority carrier lifetime below 2 nanoseconds. The sublayers may have a different composition from each other.