AMD since Aug 2008
Senior Member of Technical Staff
Sun Microsystems Apr 2008 - Aug 2008
MTS/Verification Lead
Montalvo Systems - San Francisco Bay Area Oct 2006 - Apr 2008
Verification Lead
Sierra Logic - Sacramento, California Area Apr 2003 - Oct 2006
ASIC Verification Engineer
Allegro Networks - San Francisco Bay Area Apr 2001 - Mar 2003
Verification Lead
Education:
Villanova University 1996 - 1998
Anna University 1992 - 1996
Skills:
Verilog Asic Soc Debugging Functional Verification Systemverilog Perl C Processors Firmware Simulations C++ Open Verification Methodology Arm Hardware Architecture Rtl Design Rtl Coding Project Planning Semiconductors Shell Scripting Linux Power Management Low Power Design Dft Static Timing Analysis Vlsi Ovm