Shawn T. Walsh - Richardson TX John E. Campbell - Plano TX Somit Joshi - Dallas TX James B. Friedmann - Dallas TX Michael J. McGranaghan - Dallas TX Janice D. Makos - McKinney TX Arun Sivasothy - Dallas TX Troy A. Yocum - Plano TX Jaideep Mavoori - Richardson TX Wayne A. Bather - Plano TX Joe G. Tran - Irving TX Michelle L. Hartsell - Plano TX Gregory B. Shinn - Dallas TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2176
US Classification:
438690, 438691, 438692
Abstract:
A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.
Chemical Mechanical Polishing Method And Apparatus
Joe G. Tran - Flower Mound TX, US Chad J. Kaneshige - McKinney TX, US Brian K. Kirkpatrick - Allen TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/302
US Classification:
438692, 1563451
Abstract:
A method for removing material from the surface of a semiconductor wafer with a chemical mechanical polishing process is described. The method uses a polishing pad on which a line-pattern of grooves is formed. The pattern comprises orderly spaced grooved-area and area without grooves. The method combines information of the surface topography of the wafer, the nature of the material to be removed, and the available groove pattern on the surface of the polishing pad to generate a process recipe in which the resident time of portions of the semiconductor wafer spends at the grooved and un-grooved areas of the polishing pad during the chemical mechanical polishing process is pre-determined.
The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer over gate structures located over a microelectronics substrate wherein the gate structures include sidewall spacers and have a doped region located between them. A protective layer is placed over the capping layer and the doped region , and a portion of the protective layer and capping layer that are located over the gate structures are removed to expose a top surface of the gate structures. A remaining portion of the protective layer and capping layer remains over the doped region. With the top surface of the gate structures exposed, metal is incorporated into the gate structures to form gate electrodes.
The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a spacer material over gate electrodes that are, in turn, located over a microelectronics substrate. The gate electrodes have a doped region located between them. A portion of the spacer material is removed with a chemical/mechanical process using a slurry that is selective to a portion of the spacer material. The method further comprises etching a remaining portion of the spacer material to form spacer sidewalls on the gate electrodes. The etching exposes a surface of the gate electrodes and leaves a portion of the spacer material over the doped region. Metal is then incorporated into the gate electrodes to form silicided gate electrodes.
Method Of Simultaneously Siliciding A Polysilicon Gate And Source/Drain Of A Semiconductor Device, And Related Device
Freidoon Mehrad - Plano TX, US Shaofeng Yu - Plano TX, US Steven A. Vitale - Murphy TX, US Joe G. Tran - Flower Mound TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/8234
US Classification:
438275, 438692, 438197
Abstract:
A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
Fusi Integration Method Using Sog As A Sacrificial Planarization Layer
Yaw S. Obeng - Frisco TX, US Ping Jiang - Plano TX, US Joe G. Tran - Flower Mound TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/44
US Classification:
438581, 438583, 438663, 257E29156
Abstract:
A method for making a transistor that includes using a transition metal nitride layer and/or a SOG layer to protect the source/drain regions from silicidation during the silicidation of the gate electrode. The SOG layer is planarized to expose the transition metal nitride layer or the gate electrode before the gate silicidation process. If a transition metal nitride layer is used, then it is removed from the top of the gate electrode before the full silicidation of the gate electrode.
Fusi Integration Method Using Sog As A Sacrificial Planarization Layer
Yaw S. Obeng - Frisco TX, US Ping Jiang - Plano TX, US Joe G. Tran - Flower Mound TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/44
US Classification:
438581, 438583, 438683, 257E29156
Abstract:
A method for making a transistor that includes using a transition metal nitride layer and/or a SOG layer to protect the source/drain regions from silicidation during the silicidation of the gate electrode. The SOG layer is planarized to expose the transition metal nitride layer or the gate electrode before the gate silicidation process. If a transition metal nitride layer is used, then it is removed from the top of the gate electrode before the full silicidation of the gate electrode.
Fusi Integration Method Using Sog As A Sacrificial Planarization Layer
Yaw S. Obeng - Frisco TX, US Ping Jiang - Plano TX, US Joe G. Tran - Flower Mound TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/28 H01L 21/44
US Classification:
438581, 438664, 438682, 438683, 257E29156
Abstract:
A method for making a transistor that includes using a transition metal nitride layer and/or a SOG layer to protect the source/drain regions from silicidation during the silicidation of the gate electrode. The SOG layer is planarized to expose the transition metal nitride layer or the gate electrode before the gate silicidation process. If a transition metal nitride layer is used, then it is removed from the top of the gate electrode before the full silicidation of the gate electrode.
Name / Title
Company / Classification
Phones & Addresses
Joe Tran Manager
T Mobile Huntington Beach Radiotelephone Communications
8112 Talbert Ave, Huntington Beach, CA 92646
Joe Tran President
Saturn Systems Inc Wood Office and Store Fixtures, Partitions, S...
15916 S Figueroa St, Gardena, CA 90248 Website: saturnwalls.com,
Joe Tran Owner
Jennifer & Joe Tran Farmers Insurance Agents, Brokers, and Service
8900 Bolsa Ave Ste E, Westminster, CA 92683
Joe Tran Manager
Meineke Car Care Ctr General Automotive Repair Shops
3055 Kingswood Blvd, Grand Prairie, TX 75052 Website: meineke.com
Joe Tran Manager
Mks Instruments Inc Industrial Instruments for Measurement, Displ...
789 N Grove Rd, Richardson, TX 75081 Website: mksinst.com
Joe Tran Sales Executive
Mks Instruments Inc Industrial Instruments for Measurement, Displ...
789 N Grove Rd, Richardson, TX 75081
Joe Tran Owner
Hallmark Cards Inc Gift, Novelty, and Souvenir Shops
Medical School Baylor College of Medicine Graduated: 2000
Procedures:
Lumbar Puncture
Conditions:
Appendicitis Croup Epilepsy Pneumonia Skin and Subcutaneous Infections
Languages:
English
Description:
Dr. Tran graduated from the Baylor College of Medicine in 2000. He works in Houston, TX and specializes in Hospitalist and Pediatrics. Dr. Tran is affiliated with Texas Childrens Hospital.