Joe D Tran

age ~83

from Oklahoma City, OK

Also known as:
  • Joe Quana Tran
  • Joe M Tran
  • Quang Dinh Tran
  • Quang D Tran
  • Quan V Tran

Joe Tran Phones & Addresses

  • Oklahoma City, OK
  • 7707 Pittsford Ln, Arlington, TX 76002 • 8174688396
  • 4979 Garden Grove Rd, Grand Prairie, TX 75052 • 9726470725
  • Mission Viejo, CA
  • Westminster, CA
  • Santa Ana, CA

Work

  • Company:
    joe
  • Address:
    222 S May, Oklahoma City, OK 73159
  • Phones:
    4052322145

Us Patents

  • Shallow Trench Isolation Planarization Using Self Aligned Isotropic Etch

    view source
  • US Patent:
    6686283, Feb 3, 2004
  • Filed:
    Feb 4, 2000
  • Appl. No.:
    09/498083
  • Inventors:
    Shawn T. Walsh - Richardson TX
    John E. Campbell - Plano TX
    Somit Joshi - Dallas TX
    James B. Friedmann - Dallas TX
    Michael J. McGranaghan - Dallas TX
    Janice D. Makos - McKinney TX
    Arun Sivasothy - Dallas TX
    Troy A. Yocum - Plano TX
    Jaideep Mavoori - Richardson TX
    Wayne A. Bather - Plano TX
    Joe G. Tran - Irving TX
    Michelle L. Hartsell - Plano TX
    Gregory B. Shinn - Dallas TX
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H01L 2176
  • US Classification:
    438690, 438691, 438692
  • Abstract:
    A method for forming planar isolation structures for integrated circuits. A etch barrier is formed over the isolation fill material and an etch back is performed to remove material above unetched portions of the substrate. The exposed fill material is etched and planarized to form a planar isolation structure.
  • Chemical Mechanical Polishing Method And Apparatus

    view source
  • US Patent:
    7186651, Mar 6, 2007
  • Filed:
    Oct 30, 2003
  • Appl. No.:
    10/697676
  • Inventors:
    Joe G. Tran - Flower Mound TX, US
    Chad J. Kaneshige - McKinney TX, US
    Brian K. Kirkpatrick - Allen TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H01L 21/302
  • US Classification:
    438692, 1563451
  • Abstract:
    A method for removing material from the surface of a semiconductor wafer with a chemical mechanical polishing process is described. The method uses a polishing pad on which a line-pattern of grooves is formed. The pattern comprises orderly spaced grooved-area and area without grooves. The method combines information of the surface topography of the wafer, the nature of the material to be removed, and the available groove pattern on the surface of the polishing pad to generate a process recipe in which the resident time of portions of the semiconductor wafer spends at the grooved and un-grooved areas of the polishing pad during the chemical mechanical polishing process is pre-determined.
  • Method To Obtain Fully Silicided Poly Gate

    view source
  • US Patent:
    7396716, Jul 8, 2008
  • Filed:
    Aug 11, 2005
  • Appl. No.:
    11/201924
  • Inventors:
    Freidoon Mehrad - Plano TX, US
    Shaofeng Yu - Plano TX, US
    Joe G. Tran - Flower Mound TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H01L 21/311
  • US Classification:
    438230, 438303, 438592, 438595, 257E29161, 257E21199
  • Abstract:
    The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer over gate structures located over a microelectronics substrate wherein the gate structures include sidewall spacers and have a doped region located between them. A protective layer is placed over the capping layer and the doped region , and a portion of the protective layer and capping layer that are located over the gate structures are removed to expose a top surface of the gate structures. A remaining portion of the protective layer and capping layer remains over the doped region. With the top surface of the gate structures exposed, metal is incorporated into the gate structures to form gate electrodes.
  • Method To Obtain Fully Silicided Poly Gate

    view source
  • US Patent:
    7498264, Mar 3, 2009
  • Filed:
    Jul 7, 2005
  • Appl. No.:
    11/176725
  • Inventors:
    Freidoon Mehard - Plano TX, US
    Joe G. Tran - Flower Mound TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H01L 21/302
    H01L 21/461
  • US Classification:
    438692, 438592, 438595, 438622, 257E21593, 257E2123
  • Abstract:
    The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a spacer material over gate electrodes that are, in turn, located over a microelectronics substrate. The gate electrodes have a doped region located between them. A portion of the spacer material is removed with a chemical/mechanical process using a slurry that is selective to a portion of the spacer material. The method further comprises etching a remaining portion of the spacer material to form spacer sidewalls on the gate electrodes. The etching exposes a surface of the gate electrodes and leaves a portion of the spacer material over the doped region. Metal is then incorporated into the gate electrodes to form silicided gate electrodes.
  • Method Of Simultaneously Siliciding A Polysilicon Gate And Source/Drain Of A Semiconductor Device, And Related Device

    view source
  • US Patent:
    7727842, Jun 1, 2010
  • Filed:
    Apr 27, 2007
  • Appl. No.:
    11/741519
  • Inventors:
    Freidoon Mehrad - Plano TX, US
    Shaofeng Yu - Plano TX, US
    Steven A. Vitale - Murphy TX, US
    Joe G. Tran - Flower Mound TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H01L 21/8234
  • US Classification:
    438275, 438692, 438197
  • Abstract:
    A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.
  • Fusi Integration Method Using Sog As A Sacrificial Planarization Layer

    view source
  • US Patent:
    7732312, Jun 8, 2010
  • Filed:
    Jan 24, 2006
  • Appl. No.:
    11/338028
  • Inventors:
    Yaw S. Obeng - Frisco TX, US
    Ping Jiang - Plano TX, US
    Joe G. Tran - Flower Mound TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H01L 21/44
  • US Classification:
    438581, 438583, 438663, 257E29156
  • Abstract:
    A method for making a transistor that includes using a transition metal nitride layer and/or a SOG layer to protect the source/drain regions from silicidation during the silicidation of the gate electrode. The SOG layer is planarized to expose the transition metal nitride layer or the gate electrode before the gate silicidation process. If a transition metal nitride layer is used, then it is removed from the top of the gate electrode before the full silicidation of the gate electrode.
  • Fusi Integration Method Using Sog As A Sacrificial Planarization Layer

    view source
  • US Patent:
    7732313, Jun 8, 2010
  • Filed:
    Jan 5, 2009
  • Appl. No.:
    12/348660
  • Inventors:
    Yaw S. Obeng - Frisco TX, US
    Ping Jiang - Plano TX, US
    Joe G. Tran - Flower Mound TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H01L 21/44
  • US Classification:
    438581, 438583, 438683, 257E29156
  • Abstract:
    A method for making a transistor that includes using a transition metal nitride layer and/or a SOG layer to protect the source/drain regions from silicidation during the silicidation of the gate electrode. The SOG layer is planarized to expose the transition metal nitride layer or the gate electrode before the gate silicidation process. If a transition metal nitride layer is used, then it is removed from the top of the gate electrode before the full silicidation of the gate electrode.
  • Fusi Integration Method Using Sog As A Sacrificial Planarization Layer

    view source
  • US Patent:
    7943499, May 17, 2011
  • Filed:
    Oct 21, 2009
  • Appl. No.:
    12/603169
  • Inventors:
    Yaw S. Obeng - Frisco TX, US
    Ping Jiang - Plano TX, US
    Joe G. Tran - Flower Mound TX, US
  • Assignee:
    Texas Instruments Incorporated - Dallas TX
  • International Classification:
    H01L 21/28
    H01L 21/44
  • US Classification:
    438581, 438664, 438682, 438683, 257E29156
  • Abstract:
    A method for making a transistor that includes using a transition metal nitride layer and/or a SOG layer to protect the source/drain regions from silicidation during the silicidation of the gate electrode. The SOG layer is planarized to expose the transition metal nitride layer or the gate electrode before the gate silicidation process. If a transition metal nitride layer is used, then it is removed from the top of the gate electrode before the full silicidation of the gate electrode.
Name / Title
Company / Classification
Phones & Addresses
Joe Tran
Manager
T Mobile Huntington Beach
Radiotelephone Communications
8112 Talbert Ave, Huntington Beach, CA 92646
Joe Tran
President
Saturn Systems Inc
Wood Office and Store Fixtures, Partitions, S...
15916 S Figueroa St, Gardena, CA 90248
Website: saturnwalls.com,
Joe Tran
Owner
Jennifer & Joe Tran Farmers
Insurance Agents, Brokers, and Service
8900 Bolsa Ave Ste E, Westminster, CA 92683
Joe Tran
Manager
Meineke Car Care Ctr
General Automotive Repair Shops
3055 Kingswood Blvd, Grand Prairie, TX 75052
Website: meineke.com
Joe Tran
Manager
Mks Instruments Inc
Industrial Instruments for Measurement, Displ...
789 N Grove Rd, Richardson, TX 75081
Website: mksinst.com
Joe Tran
Sales Executive
Mks Instruments Inc
Industrial Instruments for Measurement, Displ...
789 N Grove Rd, Richardson, TX 75081
Joe Tran
Owner
Hallmark Cards Inc
Gift, Novelty, and Souvenir Shops
12221 Merit Dr # 110, Dallas, TX 75251
Joe Tran
Owner
Farmer Insurance
Insurance Agent/Broker
9550 Bolsa Ave, Westminster, CA 92683
7145311741

Medicine Doctors

Joe Tran Photo 1

Joe Q. Tran

view source
Specialties:
Hospitalist, Pediatrics
Work:
Texas Childrens Hospital Pediatric
6621 Fannin St STE 1-1481, Houston, TX 77030
8328245497 (phone), 8328255424 (fax)
Education:
Medical School
Baylor College of Medicine
Graduated: 2000
Procedures:
Lumbar Puncture
Conditions:
Appendicitis
Croup
Epilepsy
Pneumonia
Skin and Subcutaneous Infections
Languages:
English
Description:
Dr. Tran graduated from the Baylor College of Medicine in 2000. He works in Houston, TX and specializes in Hospitalist and Pediatrics. Dr. Tran is affiliated with Texas Childrens Hospital.

Classmates

Joe Tran Photo 2

Joe Tran

view source
Schools:
West Elementary School Grand Prairie TX 2006-2010
Community:
Chase Labudda, Laura Atkinson, Stephen Johnson
Joe Tran Photo 3

J.E.B. Stuart High School...

view source
Graduates:
Laurie Somers (1969-1973),
Cindy Hester (1979-1983),
Joe Tran (1992-1996),
Barbara Barton (1962-1966)
Joe Tran Photo 4

Northwest High School, Wi...

view source
Graduates:
Mark Beutel (1985-1989),
Mark Flippin (1987-1991),
Joe B (1978-1982),
Joe Tran (1984-1988)
Joe Tran Photo 5

Serrano Middle School, Sa...

view source
Graduates:
Joseph Tran (1999-2003),
Sheryl Cunningham (1998-1999),
Marie Vega (1973-1975),
Katrina Hernandez (1996-2000),
Timothy Ellis (1981-1983)
Joe Tran Photo 6

Our Lady of Fatima School...

view source
Graduates:
Jamie Turner (1976-1979),
Joe Tran (1980-1984),
Caryn Fahey (1992-2002),
Dianne McReavy (1968-1973)
Joe Tran Photo 7

Aptakisic Junior High Sch...

view source
Graduates:
Lauren Fonjemie (2000-2004),
Joseph Tran (2000-2004),
Rachel Lewinthal (1999-2003),
Mina Mineva (1999-2003),
Pamela England (1995-1998)
Joe Tran Photo 8

Hamilton Junior High Scho...

view source
Graduates:
Joseph Tran (2000-2004),
Raymond Russo (1976-1979),
Kristine Hovey (1984-1988),
Roberta Castro (1973-1977),
Darrell Parker (1999-2003)
Joe Tran Photo 9

Kester Elementary School,...

view source
Graduates:
Joseph Tran (1987-1993),
Kenneth Osorio (1986-1992),
Paris Bradburd (1976-1978),
Anthony Rettinger (1951-1953)

Youtube

"Replay" Cover by Joe Tran

EXPAND FOR MORE INFO Facebook: www.facebook.com Twitter: www....

  • Category:
    Music
  • Uploaded:
    01 Jun, 2010
  • Duration:
    3m 19s

Joe Tran'z guillotine

sam houston tournament

  • Category:
    Sports
  • Uploaded:
    19 Dec, 2007
  • Duration:
    54s

Pamela Jean - Simple Man Cover (Lynyrd Skynyr...

EXPAND FOR MORE INFO Pamela Jean performing live at Beachside...

  • Category:
    Music
  • Uploaded:
    28 Feb, 2011
  • Duration:
    6m 39s

Spiritclips "Indivisible" Behind the Scenes L...

Actor Joe Tran stars as the Vietnamese guard in "Indivisible", a Spiri...

  • Category:
    Entertainment
  • Uploaded:
    13 Aug, 2009
  • Duration:
    1m

Joe Tran'z Take down

sam houston tournament

  • Category:
    Sports
  • Uploaded:
    19 Dec, 2007
  • Duration:
    1m 39s

joe tran - the imitation

Joe Tran Imitates Nhu and Charlie

  • Category:
    Nonprofits & Activism
  • Uploaded:
    02 Jun, 2008
  • Duration:
    4m 30s

Flickr

Plaxo

Joe Tran Photo 15

Joe Tran

view source
General DataTech

Facebook

Joe Tran Photo 16

Joe Tran

view source
Joe Tran Photo 17

Joe Tran

view source
Joe Tran Photo 18

Gunny Joe Tran

view source
Joe Tran Photo 19

Joe Tran

view source
Joe Tran Photo 20

Joe Tran

view source
Joe Tran Photo 21

Joe Dung Tran

view source
Joe Tran Photo 22

Joe Tran

view source
Joe Tran Photo 23

Joe Tran Tran Nguyen

view source

Myspace

Joe Tran Photo 24

joe tran

view source
Locality:
arlington, Texas
Gender:
Male
Birthday:
1941
Joe Tran Photo 25

Joe Tran

view source
Locality:
Escondido, California
Gender:
Male
Birthday:
1943
Joe Tran Photo 26

Joe Tran

view source
Locality:
California
Gender:
Male
Birthday:
1949
Joe Tran Photo 27

Joe Tran

view source
Locality:
SEATTLE, Washington
Gender:
Male
Birthday:
1944
Joe Tran Photo 28

joe tran

view source
Locality:
SAINT PAUL, Minnesota
Gender:
Male
Birthday:
1947
Joe Tran Photo 29

Joe Tran

view source
Locality:
ST.LOUIS, MISSOURI
Gender:
Male
Birthday:
1948
Joe Tran Photo 30

Joe Tran

view source

Googleplus

Joe Tran Photo 31

Joe Tran

Work:
United States Navy - Petty Officer 2nd Class (2006)
Education:
American Public University System - Information Systems Security
Tagline:
"Inter Arma Enim Silent Legis"
Joe Tran Photo 32

Joe Tran

Education:
San José State University
Tagline:
“Most people are other people. Their thoughts are someone else's opinions, their lives a mimicry, their passions a quotation."
Joe Tran Photo 33

Joe Tran

Education:
Washington State University - Doctor of Pharmacy (Pharm D)
Joe Tran Photo 34

Joe Tran

Education:
University College London - Biological sciences
Joe Tran Photo 35

Joe Tran

Lived:
Mission Viejo, CA
Littleton, Colorado
Joe Tran Photo 36

Joe Tran

Work:
Banking academy - Student
Joe Tran Photo 37

Joe Tran

Joe Tran Photo 38

Joe Tran


Get Report for Joe D Tran from Oklahoma City, OK, age ~83
Control profile