Joel F Cook

US Patent:

6821899, Nov 23, 2004

Filed:

Mar 14, 2003

Appl. No.:

10/390520

Inventors:

Shrikant P. Lohokare - Fremont CA
David Hemker - San Jose CA
Joel M. Cook - Warrenton VA

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21311

US Classification:

438697

Abstract:

A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion includes a localized non-uniformity. An additional layer is formed on the overburden portion. The additional layer and the overburden portion are planarized. The planarizing process substantially entirely removes the additional layer.

US Patent:

6939796, Sep 6, 2005

Filed:

Mar 14, 2003

Appl. No.:

10/390117

Inventors:

Shrikant P. Lohokare - Fremont CA, US
David Hemker - San Jose CA, US
Joel M. Cook - Warrenton VA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L021/4763

US Classification:

438626, 438631, 438633, 438692, 216 67, 216 78

Abstract:

A system and method for planarizing a patterned semiconductor substrate includes receiving a patterned semiconductor substrate. The patterned semiconductor substrate having a conductive interconnect material filling multiple of features in the pattern. The conductive interconnect material having an overburden portion. The overburden portion having a localized non-uniformity. A bulk portion of the overburden portion is removed to planarize the overburden portion. The substantially locally planarized overburden portion is mapped to determine a global non-uniformity. The substantially locally planarized overburden portion is etched to substantially remove the global non-uniformity.

US Patent:

7192875, Mar 20, 2007

Filed:

Oct 29, 2004

Appl. No.:

10/975947

Inventors:

Joel M. Cook - Warrenton VA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21/302

US Classification:

438706, 216 58, 216 79, 438707, 438710, 438719

Abstract:

Processes for treating a morphologically-modified surface of a silicon upper electrode of a plasma processing chamber include exposing the surface to a gas composition containing at least one gas-phase halogen fluoride. The gas composition is effective to remove silicon from the morphologically-modified surface and restore the surface state.

US Patent:

7358186, Apr 15, 2008

Filed:

Dec 12, 2003

Appl. No.:

10/735216

Inventors:

Yezdi Dordi - Palo Alto CA, US
John Boyd - Atascadero CA, US
William Thie - Mountain View CA, US
Bob Maraschin - Cupertino CA, US
Fred C. Redeker - Fremont CA, US
Joel M. Cook - Warrenton VA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21/44
B05C 5/12

US Classification:

438678, 427 98, 118 58, 118603

Abstract:

Broadly speaking, a method and an apparatus are provided for depositing a material on a semiconductor wafer (“wafer”). More specifically, the method and apparatus provide for selective heating of a surface of the wafer exposed to an electroless plating solution. The selective heating is provided by applying radiant energy to the wafer surface. The selective heating of the wafer surface causes a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase at the interface in turn causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source.

US Patent:

8490573, Jul 23, 2013

Filed:

Dec 14, 2010

Appl. No.:

12/968114

Inventors:

Yezdi Dordi - Palo Alto CA, US
John Boyd - Atascadero CA, US
William Thie - Mountain View CA, US
Bob Maraschin - Cupertino CA, US
Fred C. Redeker - Fremont CA, US
Joel M. Cook - Warrenton VA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

B05C 3/02
B05D 1/18

US Classification:

118407, 4274301

Abstract:

Broadly speaking, a method and an apparatus are provided for depositing a material on a semiconductor wafer (“wafer”). More specifically, the method and apparatus provide for selective heating of a surface of the wafer exposed to an electroless plating solution. The selective heating is provided by applying radiant energy to the wafer surface. The selective heating of the wafer surface causes a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase at the interface in turn causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source.

US Patent:

20080153291, Jun 26, 2008

Filed:

Mar 7, 2008

Appl. No.:

12/044537

Inventors:

Yezdi Dordi - Palo Alto CA, US
John Boyd - Atascadero CA, US
William Thie - Mountain View CA, US
Bob Maraschin - Cupertino CA, US
Fred C. Redeker - Fremont CA, US
Joel M. Cook - Warrenton VA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21/44
C23C 16/00

US Classification:

438678, 118642, 257E21476

Abstract:

Broadly speaking, a method and an apparatus are provided for depositing a material on a semiconductor wafer (“wafer”). More specifically, the method and apparatus provide for selective heating of a surface of the wafer exposed to an electroless plating solution. The selective heating is provided by applying radiant energy to the wafer surface. The selective heating of the wafer surface causes a temperature increase at an interface between the wafer surface and the electroless plating solution. The temperature increase at the interface in turn causes a plating reaction to occur at the wafer surface. Thus, material is deposited on the wafer surface through an electroless plating reaction that is initiated and controlled by varying the temperature of the wafer surface using an appropriately defined radiant energy source.