Joelle H Sharp

US Patent:

6391699, May 21, 2002

Filed:

Jun 5, 2000

Appl. No.:

09/586720

Inventors:

Gordon K. Madson - Herriman UT
Joelle Sharp - Herriman UT

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 218238

US Classification:

438212, 257328

Abstract:

A method of creating a thermally grown oxide of any thickness at the bottom of a silicon trench. A dielectric (e. g. oxide) pillar of a predetermined thickness is formed on a semiconductor substrate. A selective epitaxial growth (SEG) process is used to form an epitaxial layer around and over the oxide pillars. A trench is patterned and etched through the SEG layer and in alignment with the oxide pillar such that the trench terminates at the top of the oxide pillar.

US Patent:

6576954, Jun 10, 2003

Filed:

Feb 6, 2002

Appl. No.:

10/071792

Inventors:

Gordon K. Madson - Herriman UT
Joelle Sharp - Herriman UT

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 2976

US Classification:

257330, 438270

Abstract:

A method of creating a thermally grown oxide of any thickness at the bottom of a silicon trench. A dielectric (e. g. oxide) pillar of a predetermined thickness is formed on a semiconductor substrate. A selective epitaxial growth (SEG) process is used to form an epitaxial layer around and over the oxide pillars. A trench is patterned and etched through the SEG layer and in alignment with the oxide pillar such that the trench terminates at the top of the oxide pillar.

US Patent:

6825087, Nov 30, 2004

Filed:

Nov 24, 1999

Appl. No.:

09/448884

Inventors:

Joelle Sharp - Herriman UT
Gordon K. Madson - Riverton UT

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 21336

US Classification:

438296, 438424

Abstract:

A method of forming a trench in a substrate or in an epitaxial layer, previously grown over the semiconductor substrate, wherein an anneal step, using hydrogen gas results in rounded corners without the need for a rounding etch or any other processing steps to round the corners.

US Patent:

7553740, Jun 30, 2009

Filed:

May 26, 2005

Appl. No.:

11/140567

Inventors:

Joelle Sharp - Herriman UT, US
Gordon K. Madson - Herriman UT, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 21/76

US Classification:

438424, 257328, 257330, 257331, 438429

Abstract:

A field effect transistor is formed as follows. Openings are formed in a masking layer extending over a surface of a silicon region. A trench is formed in the silicon region through each opening in the masking layer. A layer of silicon is formed along sidewalls and bottom of each trench and along masking layer sidewalls which define each opening. The masking layer is removed to expose surface areas of the silicon region underlying the masking layer and to expose sidewalls of the layer of silicon to thereby form contact openings over the surface of the silicon region. A contact layer is formed to electrically contact the exposed surface areas of the silicon region and the exposed sidewalls of the layer of silicon.

US Patent:

7564096, Jul 21, 2009

Filed:

Feb 9, 2007

Appl. No.:

11/673487

Inventors:

Qi Wang - Sandy UT, US
Ming-Huang Huang - Madison WI, US
Joelle Sharp - Herriman UT, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 29/76
H01L 29/94
H01L 31/062
H01L 31/113
H01L 31/119
H01L 29/06
H01L 31/0328
H01L 31/0336
H01L 31/072
H01L 31/109
H01L 29/22
H01L 33/00

US Classification:

257330, 257 13, 257 14, 257 15, 257 16, 257 17, 257 18, 257 19, 257 20, 257 21, 257 22, 257 23, 257 24, 257 25, 257 95, 257328, 257329, 257331, 257332, 257333, 257334, 257341, 257401, 257E29127, 257E29128

Abstract:

A field effect transistor (FET) includes a semiconductor region of a first conductivity type and a well region of a second conductivity type extending over the semiconductor region. A gate electrode is adjacent to but insulated from the well region, and a source region of the first conductivity type is in the well region. A heavy body region is in electrical contact with the well region, and includes a material having a lower energy gap than the well region.

US Patent:

7754567, Jul 13, 2010

Filed:

Jun 16, 2009

Appl. No.:

12/485290

Inventors:

Qi Wang - Sandy UT, US
Ming-Huang Huang - Madison WI, US
Joelle Sharp - Herriman UT, US

Assignee:

Fairchild Semiconductor Corporation - South Portland ME

International Classification:

H01L 21/336

US Classification:

438270, 257E2141

Abstract:

A method for forming a field effect transistor (FET) includes the following steps. A well region of a first conductivity type is formed in a semiconductor region of a second conductivity type. A gate electrode is formed adjacent to but insulated from the well region. A source region of the second conductivity type is formed in the well region. A heavy body recess is formed extending into and terminating within the well region adjacent the source region. The heavy body recess is at least partially filled with a heavy body material having a lower energy gap than the well region.

US Patent:

8039401, Oct 18, 2011

Filed:

Dec 10, 2008

Appl. No.:

12/332326

Inventors:

Qi Wang - Sandy UT, US
Joelle Sharp - Herriman UT, US
Minhua Li - Sandy UT, US
Hui Chen - South Jordan UT, US

Assignee:

Fairchild Semiconductor Corporation - So. Portland ME

International Classification:

H01L 21/30
H01L 21/46
H01L 21/20
H01L 21/36
H01L 21/311

US Classification:

438700, 438694, 438455, 438478, 257E21088, 257E21567, 257E21214, 257E21599

Abstract:

A first and a second substrate are bonded together to thereby form a unitary hybrid substrate. Predefined portions of the first substrate are removed to form openings in the first substrate through which surface regions of the second substrate are exposed. A selective epitaxial growth process that is selective with respect to the crystalline orientations of the first and second substrates is carried out to thereby form epitaxial silicon from the exposed surfaces of the second substrate but not from exposed surfaces of the first substrate. The epitaxial silicon formed from the exposed surfaces of the second substrate has the same crystalline orientation as the second substrate.

US Patent:

20010034109, Oct 25, 2001

Filed:

May 1, 2001

Appl. No.:

09/846872

Inventors:

Gordon Madson - Riverton UT, US
Joelle Sharp - Herriman UT, US

International Classification:

H01L021/76

US Classification:

438/412000, 438/421000, 438/424000, 438/425000, 438/426000

Abstract:

A method of increasing trench density for semiconductor devices such as, for example, trench MOSFETs. Trenches are formed in a substrate with mesas interposed between the trenches. The initial width of the mesas are made less than target width so that a reduction in trench pitch can be realized. After a silicon layer is grown inside the trenches, the width of the mesas is increased to a final width that is two times the thickness of the silicon layer. The thickness of the silicon layer is precalculated so that it is of sufficient thickness to ensure compliance with the target mesa width.