Johan N Knall

US Patent:

6635556, Oct 21, 2003

Filed:

May 17, 2001

Appl. No.:

09/859282

Inventors:

Scott B. Herner - Palo Alto CA
James M. Cleeves - Redwood City CA
Johan Knall - Sunnyvale CA

Assignee:

Matrix Semiconductor, Inc. - Santa Clara CA

International Classification:

H01L 2120

US Classification:

438488, 438916

Abstract:

A method of making a silicon-based electronic device is provided. The method includes, for example, the steps of forming a doped silicon layer on a surface of a substrate material and forming an undoped silicon capping layer on the doped silicon layer. The thin âcappingâ layers of undoped silicon prevent outgassing of the dopants underneath the cap. In this manner, the next deposition of doped silicon is not subject to autodoping by the previous doped silicon deposition.

US Patent:

6710525, Mar 23, 2004

Filed:

Oct 19, 1999

Appl. No.:

09/421781

Inventors:

Jueng Gil Lee - Cupertino CA
Christopher J. Spindt - Menlo Park CA
Johan Knall - Sunnyvale CA
Matthew A. Bonn - Saratoga CA
Kishore K. Chakravorty - San Jose CA

Assignee:

Candescent Technologies Corporation - San Jose CA
Candescent Intellectual Property Services, Inc. - Los Gatos CA

International Classification:

H01J 102

US Classification:

313309, 313495, 313311, 313306

Abstract:

An electrode structure for a display that includes lower electrodes and upper electrodes. In one embodiment, lower and upper electrodes are formed of either an aluminum alloy or a silver alloy. In another embodiment, upper and lower electrodes are formed using a metal alloy layer over which a cladding layer is deposited. A silicon nitride passivation layer is used to protect the upper electrodes from damage in subsequent process steps. Various other materials and structures are also disclosed that protect the upper electrodes from damage in subsequent process steps.

US Patent:

6764366, Jul 20, 2004

Filed:

Oct 31, 2001

Appl. No.:

09/999755

Inventors:

Jueng Gil Lee - Cupertino CA
Christopher J. Spindt - Menlo Park CA
Johan Knall - Sunnyvale CA
Matthew A. Bonn - Saratoga CA
Kishore K. Chakravorty - San Jose CA

Assignee:

Candescent Intellectual Property Services, Inc. - Los Gatos CA
Candescent Technologies Corporation - Los Gatos CA

International Classification:

H01J 902

US Classification:

445 24, 445 50

Abstract:

An electrode structure for a display that includes lower electrodes and upper electrodes. In one embodiment, lower and upper electrodes are formed of either an aluminum alloy or a silver alloy. In another embodiment, upper and lower electrodes are formed using a metal alloy layer over which a cladding layer is deposited. A silicon nitride passivation layer is used to protect the upper electrodes from damage in subsequent process steps. Various other materials and structures are also disclosed that protect the upper electrodes from damage in subsequent process steps.

US Patent:

6780683, Aug 24, 2004

Filed:

Dec 6, 2002

Appl. No.:

10/313763

Inventors:

Mark G. Johnson - Los Altos CA
James M. Cleeves - Redwood City CA
Johan Knall - Sunnyvale CA

Assignee:

Matrix Semiconductor, Inc. - Santa Clara CA

International Classification:

H01L 2182

US Classification:

438128, 257 50

Abstract:

A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.

US Patent:

6844663, Jan 18, 2005

Filed:

May 31, 2000

Appl. No.:

09/588115

Inventors:

Jueng Gil Lee - Cupertino CA, US
Christopher J. Spindt - Menlo Park CA, US
Johan Knall - Sunnyvale CA, US
Matthew A. Bonn - Saratoga CA, US
Kishore K. Chakravorty - San Jose CA, US

Assignee:

Candescent Intellectual Property - San Jose CA

International Classification:

H01J 102

US Classification:

313309, 313495, 313310, 313311, 313306, 445 24

Abstract:

A structure for a multilayer electrode. Specifically, in one embodiment, a multilayer electrode for a flat panel display device is disclosed. The multilayer electrode comprises a metal alloy layer and a protective layer. The metal alloy layer includes neodymium having a concentration of between greater than three atomic percent and six atomic percent. The protective layer is disposed above the metal alloy layer to form a multilayer stack. The multilayer stack is etched to form the multilayer electrode.

US Patent:

7488625, Feb 10, 2009

Filed:

May 17, 2004

Appl. No.:

10/848601

Inventors:

Johan Knall - Sunnyvale CA, US

Assignee:

Sandisk 3D LLC - Milpitas CA

International Classification:

H01L 21/82

US Classification:

438131, 257E2702

Abstract:

A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.

US Patent:

20040018731, Jan 29, 2004

Filed:

Jul 21, 2003

Appl. No.:

10/624580

Inventors:

Scott Herner - Palo Alto CA, US
James Cleeves - Redwood City CA, US
Johan Knall - Sunnyvale CA, US

Assignee:

MATRIX SEMICONDUCTOR, Inc.

International Classification:

H01L021/302
H01L021/461

US Classification:

438/689000

Abstract:

A method of making a silicon-based electronic device is provided. The method includes, for example, the steps of forming a doped silicon layer on a surface of a substrate material and forming an undoped silicon capping layer on the doped silicon layer. The thin “capping” layers of undoped silicon prevent outgassing of the dopants underneath the cap. In this manner, the next deposition of doped silicon is not subject to autodoping by the previous doped silicon deposition.

US Patent:

6448708, Sep 10, 2002

Filed:

May 31, 2000

Appl. No.:

09/588118

Inventors:

Kishore K. Chakravorty - San Jose CA
Swayambu Ramani - San Jose CA
Stephanie J. Oberg - Sunnyvale CA
Johan Knall - Sunnyvale CA
Duane A. Haven - Umpqua OR
Ronald S. Besser - Ruston LA
Paul J. Louris - Mountain View CA
Arthur J. Learn - Cupertino CA
Christopher J. Spindt - Menlo Park CA
Roger W. Barton - Tofte MN

Assignee:

Candescent Intellectual Property Services, Inc. - San Jose CA

International Classification:

H01J 102

US Classification:

313495, 313309, 313336, 313351, 313310

Abstract:

A flat panel display and a method for forming a flat panel display. In one embodiment, the flat panel display includes a cathodic structure which is formed within an active area on a backplate. The cathodic structure includes a emitter electrode metal composed of strips of aluminum overlain by a layer of cladding material. The use of aluminum and cladding material to form emitter electrode metal gives emitter electrode metal segments which are highly conductive due to the high conductivity of aluminum. By using a suitable cladding material and processing steps, a bond between the aluminum and the cladding material is formed which has good electrical conductivity. In one embodiment, tantalum is used as a cladding material. Tantalum forms a bond with the overlying resistive layer which has good electrical conductivity. Thus, the resulting structure has very high electrical conductivity through the aluminum layer and high conductivity into the resistive layer.