John L Beck

Address:

7210 Hidden Hls N, San Antonio, TX 78244

VIN:

1UJCJ02P771LJ0137

Make:

Plymouth

Model:

Voyager 3dr SE 113 WB

Year:

2007

US Patent:

62090550, Mar 27, 2001

Filed:

Oct 29, 1998

Appl. No.:

9/182301

Inventors:

Christopher McCall Durham - Austin TX
Peter Juergen Klim - Austin TX
John Andrew Beck - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F13/00;3/00
7
G11C7/02
5/06

US Classification:

710131

Abstract:

For transmitting information on a plurality of integrated circuit conductive lines, n conductive lines are provided on a path in an integrated circuit. The path has first and second portions, and an interposing, transition portion. The lines have first positions with respect to one another in the first portion, and certain of the lines change relative positions in the transition portion, so that the lines have second positions with respect to one another in the second portion. The information is encoded in a format wherein no more than one of the n lines has a signal asserted thereon at a time, so that there is a reduction in noise induced among the lines.

US Patent:

60852895, Jul 4, 2000

Filed:

Jul 18, 1997

Appl. No.:

8/896475

Inventors:

Larry Edward Thatcher - Austin TX
John Beck - Austin TX
Michael Kevin Ciraula - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711118

Abstract:

An improved load data formatter and methods for improving load data formatting and for cache line data organization are disclosed. The load data formatter includes a data selection mechanism, the data selection mechanism receiving a data cache line of a predetermined organization, and the data selection mechanism further supporting adjacent word swapping in the cache line. The load data formatter further includes at least two word selectors coupled to an output of the data selection mechanism, the at least two word selectors forming a doubleword on a chosen word boundary of the cache line. In a further aspect, the predetermined organization of the cache line is provided by grouping each corresponding bit of each byte in a cache line of data together, and expanding the grouping with an organization formed by one bit from a same byte within each word. The at least two word selectors may comprise even and odd multiplexers, and the load data formatter may also include splice registers, coupled to an output of one of the at least two selectors, which provide formatting of unaligned load access across a cache line boundary.

US Patent:

57843309, Jul 21, 1998

Filed:

Dec 2, 1996

Appl. No.:

8/752981

Inventors:

John Andrew Beck - Austin TX
Terry Lee Leasure - Georgetown TX
Gus Wai-Yan Yeung - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 800

US Classification:

36523006

Abstract:

A device for accessing a specific word line in a memory array has improved noise protection by smoothing out the RC load in the word line mapping circuit. The word lines are respectively connected to rows of memory cells in the memory array, and predecoded word lines are used to decode encoded addresses which correspond to the various rows. The circuit connects the word lines to the predecoded word lines by gates which are tapped into the predecoded word lines, and the taps on a given predecoded word line are non-adjacent, to more evenly distribute the RC delay for each predecoded word line. In other words, the word lines are interspersed, out of order. The word lines can be interspersed randomly, or according to a predetermined function, such as a modulo function. The RC load for a given predecoded word line is preferably uniformly distributed along substantially the entire length of the predecoded word line.

US Patent:

49411560, Jul 10, 1990

Filed:

Mar 22, 1989

Appl. No.:

7/327027

Inventors:

Kenneth J. Stern - Austin TX
John A. Beck - Austin TX

Assignee:

Crystal Semiconductor - Austin TX

International Classification:

H04L 702

US Classification:

375118

Abstract:

A jitter attenuation circuit includes a FIFO data register (10) which is operable to receive data that is synchronized with a Write clock output therefrom synchronized with a Read clock. The data is written to the FIFO register (10) from a location determined by a Write pointer (12). The data is read out from the FIFO register (10) from a location determined by a Read pointer (14) which is clocked by a Read clock. The Read clock is synchronized with the Write clock by a phase lock loop (24). The phase lock loop (24) has a phase detector (26) which is operable to accrue phase error over intervals of 2. pi. radians such that the phase lock loop (24) virtually never loses lock as a result of phase jitter on the Write clock. The phase lock loop (24) has contained therein a digitally controlled linear oscillator (28) wherein the phase detector (26) provides a quantized output to incrementally step the digitally controlled oscillator (28) up or down in frequency to track the Write clock while attenuating jitter thereon.

US Patent:

58218505, Oct 13, 1998

Filed:

Sep 17, 1996

Appl. No.:

8/710441

Inventors:

John Andrew Beck - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G05B 100

US Classification:

3401462

Abstract:

An information handling system includes a data comparison circuit which includes a number of multi-bit comparison circuit modules, wherein each of the multi-bit comparison circuit modules includes a circuit for comparing two or more bits from a first data source with two or more bits from a second data source to produce an output indicating that the data bits from the first data source are equal to the data bits from the second data source; one or more AND gates for ANDing output signals from each of the first set of circuit modules to produce an output signal if all bits in the first data source are equal to all bits in a second data source; one or more second circuit modules for providing an output signal indicating that data bits from the first data source are unequal to corresponding data bits from the second data source; and one or more inequality combination circuits combining inequality signals from each of the second set of circuit modules to produce an output when value of data from the first data source is unequal to the value of data from the second data source. The unequal compare may typically produce a signal indicating that the selected data bits from the first data source are greater than the corresponding data bits from the second data source. Alternatively, the unequal compare can be used to indicate a less than compare condition.

US Patent:

61475084, Nov 14, 2000

Filed:

Aug 20, 1998

Appl. No.:

9/137776

Inventors:

John Andrew Beck - Austin TX
David William Boerstler - Round Rock TX
Christopher McCall Durham - Austin TX
Peter Juergen Klim - Austin TX

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H03K 1716
H03K 190948
H03K 3011

US Classification:

326 32

Abstract:

An apparatus and method for controlling the power consumption of a logic device are implemented. The power dissipation, and consequently, the speed of a complementary metal oxide semiconductor (CMOS) logic device is substantially proportional to the speed of the device. The temperature of the logic device is controlled by controlling the device speed by adjusting the threshold voltage of the metal oxide semiconductor (MOS) devices forming the logic device under control. The threshold voltage of the devices is controlled by applying a back bias voltage between the bulk material in which each device under control is fabricated, and the most positive electrode of the device. The back bias voltage value is regulated in response to the logic device temperature, thereby closing a feedback loop.

US Patent:

61337595, Oct 17, 2000

Filed:

Jun 16, 1998

Appl. No.:

9/097794

Inventors:

John Andrew Beck - Austin TX
Robert Paul Masleid - Austin TX
Thomas Robert Toms - Dripping Springs TX

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H03K 190948

US Classification:

326 98

Abstract:

A dynamic logic circuit is implemented which decouples the reset of the output from the reset of the evaluation node. An N-tree logic circuit generates a logical output signal in response to a first set of input signals. The output signal is coupled to a gate of a first n-type field effect transistor (NFET) of a parallel coupled pair of NFET devices. The parallel drains are coupled to an output of the dynamic logic circuit and the parallel sources are coupled to ground. The gate of the second NFET device of the pair is coupled to the junction of a source and drain, respectively, of a series connected p-type field effect transistor (PFET) device, and a third NFET device. The third NFET device has a source coupled to ground, and the PFET device has a drain coupled to a voltage supply. Gates of the PFET device and the third NFET device are connected together and receive a logic signal whereby the output of the dynamic logic circuit may be reset.

US Patent:

60555572, Apr 25, 2000

Filed:

Jan 8, 1997

Appl. No.:

8/780561

Inventors:

John Andrew Beck - Austin TX
James Edward Dunning - Austin TX
John Stephen Muhich - Austin TX

Assignee:

International Business Machines Corp. - Armonk NY
Motorola, Inc. - Schaumburg IL

International Classification:

G06F 750

US Classification:

708700

Abstract:

An adder (300) generates encoded outputs to conserve power. In particular, the adder provides "B2" encoded outputs which only drive one bit per every two bits at a time on conductive lines in a data processing system. A binary input is encoded by an encoder (800, 304) to generate a plurality of bits. The plurality of bits are concatenated to form a plurality of sum values. A portion of the plurality of sum values are then selectively output in response to a logic value of a carry kill signal, a carry generate signal, and a carry propagate signal.