John D Beck

US Patent:

7266626, Sep 4, 2007

Filed:

Sep 28, 2004

Appl. No.:

10/953162

Inventors:

Mason B. Cabot - San Francisco CA, US
Frank T. Hady - Portland OR, US
John C. Beck - Northboro MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/00

US Classification:

710107, 710114, 710116

Abstract:

A method and apparatus for adding an additional agent to a set of symmetric agents in a bus-based system is disclosed. In one embodiment, the number of symmetric agents in the system is fixed. An additional agent may monitor the symmetric arbitration of the symmetric agents, and at a given stage of the symmetric arbitration assert a priority agent bus request. The priority agent bus request may be shared with another priority agent. This may permit the additional agent to access the bus in a fair manner that behaves as though it were an additional symmetric agent in the system.

US Patent:

7437556, Oct 14, 2008

Filed:

Jan 21, 2004

Appl. No.:

10/763147

Inventors:

Andrew G. Tucker - Menlo Park CA, US
John T. Beck - San Jose CA, US
David S. Comay - Oakland CA, US
Andrew D. Gabriel - Fleet, GB
Ozgur C. Leonard - San Mateo CA, US
Daniel B. Price - Mountain View CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H04L 9/34
H04L 12/22
H04L 9/32

US Classification:

713164, 713165, 713166

Abstract:

In accordance with one embodiment of the present invention, there is provided a mechanism for managing and controlling global visibility of resources in zones within an operating system controlled by a single kernel instance. Embodiments enable isolation and virtualization of processes within a single image of an operating system, without requiring implementation of hardware support (such as the introduction of an additional privilege level) to isolate privileged programs, and without multiple instances of an operating system or operating system kernel for some applications.

US Patent:

20060223041, Oct 5, 2006

Filed:

Apr 1, 2005

Appl. No.:

11/096348

Inventors:

John Beck - Phoenix AZ, US
Adam Carstens - Scottsdale AZ, US

Assignee:

North Star Leadership Group, Inc. - Phoenix AZ

International Classification:

G09B 5/00

US Classification:

43430700R

Abstract:

A video game teaches a player through game play, assesses the player's learning, and determines how fast the player is learning and whether the player is learning faster. The learning assessment is used to determine how fast the player is learning, and the determination of how fast the player is learning is used to determine whether the player is learning faster. Alternatively, a video game player performs one or more attempts to overcome a challenge corresponding to the satisfaction of a predetermined game condition. A learning award is derived for each attempt where the predetermined game condition is satisfied based upon the player's performance in satisfying the game condition. A learning velocity is derived as a function of change in the learning award from a different attempt. A learning acceleration can also be derived for each attempt as a function of change in the learning velocity.

US Patent:

58838244, Mar 16, 1999

Filed:

Nov 29, 1993

Appl. No.:

8/158649

Inventors:

Ruby Bei-Loh Lee - Los Altos Hills CA
John Paul Beck - Tyngsborough MA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 738
G06F 750

US Classification:

364734

Abstract:

An apparatus that can also be used for generating the average of two integers. The apparatus can be divided into a plurality of sub-adders that operate on sub-words of the input integers in parallel. Hence, the adder can be used for adding or subtracting one set of two integers wherein each integer is of some predetermined length or a plurality of sets of two integers provided the sum of the lengths of the integers is less than or equal to this predetermined length. The apparatus can also generate the sum, or difference, of each of the sub-words divided by two. The parallel operations can be carried out in response to a single instruction. The results of the division by two are rounded in a manner that eliminates biasing of the results.

US Patent:

20190114261, Apr 18, 2019

Filed:

Apr 6, 2018

Appl. No.:

15/947020

Inventors:

- Santa Clara CA, US
MASON CABOT - San Francisco CA, US
MARK B. ROSENBLUTH - Uxbridge MA, US
JOHN BECK - Northboro MA, US

International Classification:

G06F 12/084
G06F 15/167
G06F 13/40
G06F 13/42
G06F 15/78
G06F 12/0893
G06F 12/0815
G06F 12/0811

Abstract:

A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

US Patent:

20170097888, Apr 6, 2017

Filed:

Dec 15, 2016

Appl. No.:

15/380289

Inventors:

- Santa Clara CA, US
MASON CABOT - San Francisco CA, US
MARK B. ROSENBLUTH - Uxbridge MA, US
JOHN BECK - Northboro MA, US

International Classification:

G06F 12/084
G06F 13/42
G06F 13/40
G06F 12/0811

Abstract:

A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

US Patent:

20170097889, Apr 6, 2017

Filed:

Dec 15, 2016

Appl. No.:

15/380328

Inventors:

- Santa Clara CA, US
MASON CABOT - San Francisco CA, US
MARK B. ROSENBLUTH - Uxbridge MA, US
JOHN BECK - Northboro MA, US

International Classification:

G06F 12/084
G06F 13/42
G06F 13/40
G06F 12/0811

Abstract:

A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

US Patent:

20160188466, Jun 30, 2016

Filed:

Dec 22, 2015

Appl. No.:

14/977929

Inventors:

- Santa Clara CA, US
Mason Cabot - San Francisco CA, US
Mark B. Rosenbluth - Uxbridge MA, US
John Beck - Northboro MA, US

International Classification:

G06F 12/08

Abstract:

A multi-core processor providing heterogeneous processor cores and a shared cache is presented.