John A Connor

US Patent:

6353903, Mar 5, 2002

Filed:

Oct 28, 1994

Appl. No.:

08/330768

Inventors:

Robert Dean Adams - Essex Junction VT
John Connor - Burlington VT
Donald Albert Evans - Williston VT
Luigi Ternullo, Jr. - Colchester VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

714724, 714733

Abstract:

True and complement data signals are provided to a multiplexer, which selects one of them based on a selection signal for capture by a single scannable latch in response to a clock signal. The scannable latch then provides the captured signal for testing by testing logic.

US Patent:

6459925, Oct 1, 2002

Filed:

Nov 24, 1999

Appl. No.:

09/449267

Inventors:

Morgan W. Nields - Englewood CO
John Connor - Elizabeth CO
Curtis Daly - Denver CO

Assignee:

Fischer Imaging Corporation - Denver CO

International Classification:

A61B 505

US Classification:

600427, 600440, 378 37, 128915

Abstract:

The present invention provides for x-ray imaging and ultrasound imaging of a body region of interest in a spatially correlatable manner. The resultant x-ray and ultrasound images may be combinatively employed to provide three-dimensional information regarding a location of interest within the body, and is particularly apt for use in the analysis/biopsy of potential lesions and suspicious masses in a female breast. The invention provides for direct body contact by an ultrasound imaging head, as well as targeted ultrasound imaging of a selected portion of the region from which x-ray images are obtained. A user interface system facilitates various procedures including ultrasound guided needle biopsy procedures.

US Patent:

6501293, Dec 31, 2002

Filed:

Nov 12, 1999

Appl. No.:

09/439787

Inventors:

George M. Braceras - Essex Junction VT
John Connor - Burlington VT
Patrick R. Hansen - Essex Junction VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19003

US Classification:

326 30, 326 56, 326 57, 326 58, 326 83

Abstract:

A method and apparatus for providing programmable active termination of transmission lines with substantially reduced DC power consumption.

US Patent:

6617986, Sep 9, 2003

Filed:

Sep 4, 2001

Appl. No.:

09/682449

Inventors:

John Connor - Burlington VT
Patrick R. Hansen - Essex Junction VT
Steven Leschuk - Little Silver NJ
Jason E. Rotella - Minesville NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 704

US Classification:

341 97, 341159, 341160, 341 64

Abstract:

A Sequential Gray Code to Thermometer Code decoder circuit adapted for area efficient use at each pad of an integrated circuit chip for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations. The sequential decoder for decoding a Gray code count to a T-bit Thermometer code count is constructed of a plurality (T) of cascaded decoder cells, each cell sensing the state of only one bit of the Gray code count. The decoder cells are cascaded to from decoding-latching stages each stage responsive to an individual one of single-bit changes between consecutive counts in the Gray code. Each stage contains a decoding-latching circuit adapted to detecting and latching the occurrence of one single-bit change in the Gray code.

US Patent:

6965503, Nov 15, 2005

Filed:

Sep 30, 2003

Appl. No.:

10/605441

Inventors:

John Connor - Burlington VT, US
Christopher S. Putnam - Hinesburg VT, US
Alan L. Roberts - Jericho VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H02H009/00

US Classification:

361 56

Abstract:

An ESD protection circuit including the following: one or more inverters (I, I, I), each of the one or more inverters having an input and an output; an RC network () having an output node (RCT), output node (RCT) connected with the input of at least one of said one or more inverters; a clamping device (N) joined with the output of at least one of one or more inverters (I, I, I); and a feedback device (NKP) in communication with clamping device (N) and output node (RCT) of RC network (). An RC network may include one or more resistors, and one or more decoupling capacitors. In one embodiment, feedback device (NKP) is an NFET and each of one or more inverters (I, I, I) includes a PFET and NFET pair (P/N, P/N, P/N).

US Patent:

7496398, Feb 24, 2009

Filed:

Sep 27, 2002

Appl. No.:

10/260719

Inventors:

Morgan W. Nields - Englewood CO, US
John Connor - Elizabeth CO, US
Curtis Daly - Denver CO, US

Assignee:

Hologic Inc. - Marlborough MA

International Classification:

A61B 6/02

US Classification:

600427, 600439, 600461, 378 37, 378208, 128915, 128916

Abstract:

The present invention provides for x-ray imaging and ultrasound imaging of a body region of interest in a spatially correlatable manner. The resultant x-ray and ultrasound images may be combinatively employed to provide three-dimensional information regarding a location of interest within the body, and is particularly apt for use in the analysis/biopsy of potential lesions and suspicious masses in a female breast. The invention provides for direct body contact by an ultrasound imaging head, as well as targeted ultrasound imaging of a selected portion of the region from which x-ray images are obtained. A user interface system facilitates various procedures including ultrasound guided needle biopsy procedures.

US Patent:

57967458, Aug 18, 1998

Filed:

Jul 19, 1996

Appl. No.:

8/684519

Inventors:

Robert D. Adams - Essex Junction VT
John Connor - Burlington VT
Garrett S. Koch - Cambridge VT
Luigi Ternullo - Colchester VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

371 211

Abstract:

A memory Array Built-In Self-Test (ABIST) circuit is disclosed that will test a multi-port memory array. A programmable pattern generator for the ABIST circuit allows for different R/W data operations to be performed at the same or adjacent address locations within a multi-port memory array. The programmable pattern generator comprises a data generator, a read/write controller, and an address counter, each having the same number of outputs as ports of the multi-port memory array. The programmable pattern generator also comprises a frequency controller. The data generator is programmed with the appropriate data patterns for the memory array, and the read/write controller is programmed with the appropriate read/write patterns for the memory array. The address counter is to provide the same or different addresses on each port of the multi-port array, and the frequency controller is programmed with the appropriate frequency information to determine the number of read/write operations per cell in the memory array. The combination of programmable data, programmable read/write sequences, programmable address counter, and programmable frequency allows for determistic testing of a multi-port memory array, a plurality of single-port memory arrays, or a combination thereof by providing unique read/write sequences to the same or to adjacent memory locations.

US Patent:

57400989, Apr 14, 1998

Filed:

Jun 27, 1996

Appl. No.:

8/671279

Inventors:

Robert Dean Adams - Essex Junction VT
John Connor - Burlington VT
James J. Covino - Essex Junction VT
Roy Childs Flaker - Essex Junction VT
Garrett Stephen Koch - Cambridge VT
Alan Lee Roberts - Jericho VT
Jose Roriz Sousa - Colchester VT
Luigi Ternullo - Colchester VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 1500

US Classification:

365 49

Abstract:

An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory.