John Peter Goetz

US Patent:

6449693, Sep 10, 2002

Filed:

Apr 5, 1999

Appl. No.:

09/286708

Inventors:

John W. Goetz - Underhill VT
Paul T. Gutwin - Williston VT
Stephen W. Mahin - Underhill VT
Wilbur D. Pricer - Charlotte VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711122, 711123, 711128

Abstract:

A processor system is provided that comprises a plurality of L0 caches, a processor having a plurality of execution units, and an L1 cache for caching any data and instructions used by the processor. A portion of the execution units provided are configured so that each execution unit within the portion accesses one of the L0 caches. Each of the L0 caches is accessible by only one of the portion of the execution units, and each L0 cache caches a subset of any data used by the processor which is not cacheable by any of the other L0 caches. The processor system preferably comprises an instruction dispatcher that dispatches instructions executable by the processor and that selectively designates data as cacheable by only one of the L0 caches, preferably at dispatch time.

US Patent:

6532520, Mar 11, 2003

Filed:

Sep 10, 1999

Appl. No.:

09/394965

Inventors:

Alvar A. Dean - Essex Junction VT
Marc R. Faucher - South Burlington VT
John W. Goetz - Underhill VT
Kenneth J. Goodnow - Essex Junction VT
Paul T. Gutwin - Williston VT
Stephen W. Mahin - Underhill VT
Wilbur D. Pricer - Charlotte VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1200

US Classification:

711133, 711123, 711130, 711136, 711159, 711160

Abstract:

A method and apparatus are provided for managing cache allocation for a plurality of data types in a unified cache having dynamically allocable lines for first type data and for second type data. Cache allocation is managed by counting misses to first type data and misses to second type data in the unified cache, and by determining when a difference between a number of first type data misses and a number of second type data misses crosses a preselected threshold. A replacement algorithm of the unified cache then is adjusted in response to the detected crossing of the preselected threshold, the adjusting step including increasing a replacement priority of the first type data lines in the cache. The replacement algorithm preferably is an LRU algorithm wherein the adjusting step includes incrementing an age indication of the first type data lines. Hardware for implementing the inventive cache allocation management method comprises a miss counter configured to increment its count in response to a miss to first type data signal on a first counter input and to output a first logic state on a first counter output when the counters count exceeds a first predetermined count.

US Patent:

58549137, Dec 29, 1998

Filed:

Jun 10, 1997

Appl. No.:

8/872370

Inventors:

John W. Goetz - Jericho VT
Stephen W. Mahin - Chittenden VT
John J. Bergkvist - Chittenden VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 922
G06F 9455

US Classification:

395386

Abstract:

A microprocessor which supports two distinct instruction-set architectures. The microprocessor includes a mode control unit which enables extensions and/or limitations to each of the two architectures and controls the architectural context under which the microprocessor operates. The control unit controls memory management unit (MMU) hardware that is designed to allow address translation to take place under the control of a mode bit so that the translation mechanism can be switched from one architecture to another. A single MMU translates addresses of the two distinct architectures under control of the mode bit which is also used to simultaneously inform instruction decode which architecture is being used so that instructions are properly decoded. The MMU is also capable of mapping the address translation of one architecture onto that of the other so that software written for both architectures may be multi-tasked under the control of a single operating system.

US Patent:

57846383, Jul 21, 1998

Filed:

Feb 22, 1996

Appl. No.:

8/605409

Inventors:

John Wallace Goetz - Jericho VT
John Michael Keaty - Shelburne VT
Stephen William Mahin - Underhill VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

39580043

Abstract:

A computer system supports control transfers between two architectures with different address ranges and/or different methods of calling programs which involve passing parameters, stack pointers and return addresses. Control is transferred between the architectures through a control transfer mode bit.

US Patent:

52821471, Jan 25, 1994

Filed:

Aug 2, 1991

Appl. No.:

7/739923

Inventors:

John W. Goetz - Underhill VT
David J. Hathaway - Underhill VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1560

US Classification:

364489

Abstract:

A system for optimizing a logic network including expressing the logic network as an original graph having vertices, edges which connect the vertices and which represent connections in the logic network, and inversion markings for representing inverters in the logic network; determining a fundamental cycle(s) in the original graph; sorting the determined fundamental cycle(s) according to its parity; forming a final graph by processing the fundamental cycle(s) so as to optimize inverter placement therein while maintaining the parity thereof; comparing the inversion markings of the original and final graphs to determine a set of transformation locations in the logic network; and re-configuring the logic network in accordance with the determined transformation locations.