John Michael Golio

US Patent:

55900631, Dec 31, 1996

Filed:

Jul 5, 1994

Appl. No.:

8/270948

Inventors:

John M. Golio - Chandler AZ
Robert C. Turner - Mesa AZ
Monte G. Miller - Phoenix AZ
David J. Halchin - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1700

US Classification:

364580

Abstract:

A method executed by a computer for performing numerical optimization of arbitrary functions in a computer model using parallel processors (10, 12, 14). The method initializes (20) each processor with an initial estimate of the parameter value to be optimized. The initial estimate is evaluated (22) in each processor to determine a solution. A best estimate of the parameter value from the result in each processor is selected (24), and one or more of the parallel processors with the best estimate is set to run in gradient mode while the remaining processors run in random mode (26). The estimates of the parameter value from the processors running in random mode is evaluated until a local minimum is obtained from the processor running in gradient mode (28). The process is repeated until an optimal solution is found (34).

US Patent:

48497169, Jul 18, 1989

Filed:

Aug 15, 1988

Appl. No.:

7/231922

Inventors:

John M. Golio - Chandler AZ
David A. Warren - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03B 508
H03B 518

US Classification:

331 66

Abstract:

An optical injection locking oscillator is comtemplated having a tuning device. The tuning device generates a DC voltage proportional to the resonant frequency of a modulated light used to injection lock the free running oscillator. The DC voltage is applied to a varactor capacitor within the oscillator to bring the frequency of oscillation within a close proximity to the modulating frequency of the light. This facilitates injection locking, whereas frequencies of oscillation outside a certain locking range will not facilitate injection locking. The modulated light then locks the oscillator into a desired resonant frequency. A second embodiment contemplates using a YIG oscillator regulated by a DC current generated within the tuning device.

US Patent:

53451236, Sep 6, 1994

Filed:

Jul 7, 1993

Appl. No.:

8/087245

Inventors:

Joseph Staudinger - Gilbert AZ
John M. Golio - Chandler AZ
William B. Beckwith - Chandler AZ
Jean B. Verdier - Tournefeuille, FR

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03H 1100

US Classification:

307552

Abstract:

An attenuator circuit uses single point control to adjust the attenuation levels between first and second nodes. The attenuator is set-up as a. pi. -network with a pass transistor and first and second shunt transistors. Capacitors are coupled in the drain and source conduction paths of the first and second shunt transistors for DC isolation to float the shunt transistors. A control voltage applied at the drain of the pass transistor and the gates of the first and second shunt transistors controls the attenuation level. A parallel resistor and capacitor combination at the drain of the first shunt transistor provides tuning to match the input impedance of the attenuator to the sourcing circuit.

US Patent:

49981471, Mar 5, 1991

Filed:

Jul 31, 1989

Appl. No.:

7/387050

Inventors:

William B. Beckwith - Chandler AZ
John M. Golio - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 29480
H01L 29560
H01L 29640

US Classification:

357 15

Abstract:

Overlapping gate electrodes are selectively energized to vary the electrical length and thus the resistance of the conductive path through a field effect attenuator. The electrical width can also be varied to provide additional control over the resistance.

US Patent:

54107431, Apr 25, 1995

Filed:

Jun 14, 1993

Appl. No.:

8/075621

Inventors:

Warren L. Seely - Chandler AZ
Joseph Staudinger - Gilbert AZ
John M. Golio - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04B 126

US Classification:

455326

Abstract:

A mixer separates IF components IF1, IF2 of the same frequency which are images of different frequency RF signals RF1, RF2 beating with a given LO signal. The LO signal is applied to a FET active power divider and applied to the drains of a pair of balanced FET mixing elements. The FETs for the active power divider are built from the same device structure as the FETs for the mixing elements sharing drain nodes. The RF signals are passed through a quadrature phase shifter and applied to the gates of the FET mixing elements. The mixed signals appear at the drains of FET mixing elements are applied to opposing ports of a second quadrature hybrid at whose output ports the separated IF output signals IF1, IF2 appear.

US Patent:

52201945, Jun 15, 1993

Filed:

May 4, 1991

Appl. No.:

7/697506

Inventors:

John M. Golio - Chandler AZ
Ronald J. Massey - Mesa AZ
Monte G. Miller - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2992

US Classification:

257601

Abstract:

A variable field effect capacitive device suitable for providing different amounts of capacitance in response to control signals of different magnitudes. The device includes a pair of plate electrodes and a pair of control electrodes. A semiconductor region is located between the control electrodes. The plates each make Schottky contact to the semiconductor region to form a depletion region therein which changes shape in response to changes in the magnitude of the control signals.

US Patent:

50050591, Apr 2, 1991

Filed:

May 1, 1989

Appl. No.:

7/345746

Inventors:

John M. Golio - Chandler AZ
Joseph Staudinger - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2980
H01L 2978
H03K 301

US Classification:

357 22

Abstract:

A field effect device and circuit suitable for providing an analog output signal having a magnitude which is representative of a digital input code having a sequence of bits. The device includes a plurality of gate electrodes located between an input electrode and an output electrode. The gate electrodes have unequal lengths to provide different gate widths each representative of the magnitude of a portion of an analog signal provided at the output electrode in response to a digital signal of a particular logic state, such as a logical "one", when applied to any one of the gate electrodes. Thus, the magnitude of the current conducted between the input electrode and the output electrode is responsive to the sum of the widths of the gates receiving the digital signal of a particular logic state.

US Patent:

56311753, May 20, 1997

Filed:

Jan 17, 1996

Appl. No.:

8/587434

Inventors:

James G. Gilbert - Tempe AZ
Lawrence S. Klingbeil - Chandler AZ
David J. Halchin - Chandler AZ
John M. Golio - Chandler AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 218252

US Classification:

438174

Abstract:

A field effect transistor (10) has an active layer (16) formed in a substrate (12). A gate (20) is disposed on an elevated platform (18) formed from the active layer (16). The elevated platform (18) raises the bottom surface (21) of the gate (20) relative to the top surface (34, 36) of the active region (13) on either side of the gate (20). A fabrication method for the transistor (10) forms the elevated platform (18) by etching the active region surface (44) on both sides of the gate (20) so that the bottom surface (21) of the gate (20) is elevated relative to the top surface (34) of the surrounding active region (13). The gate (20) itself and/or a patterned photoresist layer (116) may be used as a mask for performing this etch.