John F Gorman

US Patent:

7304603, Dec 4, 2007

Filed:

Feb 17, 2006

Appl. No.:

11/356997

Inventors:

John C. Reed - Centreville VA, US
John D. Gorman - Falls Church VA, US

Assignee:

Science, Engineering and Technology Associates Corporation - Arlington VA

International Classification:

G01S 13/02
G01S 13/56

US Classification:

342188, 342 22, 342 27, 342160

Abstract:

A linear FM pulse radar with Doppler processing of co-polarized and cross-polarized radar return signals isolates the target echo signal content associated with a moving pedestrian to provide high quality target echo data for standoff HCE detection based on polarimetric signature analysis. Baseband co-polarized and cross-polarized radar return signals are repeatedly and coherently integrated across numerous successive radar return pulses to create co-polarized and cross-polarized range vs. velocity (Doppler) data maps. The co-polarized data map is used to identify a moving pedestrian, and co-polarized and cross-polarized data subsets corresponding to the identified pedestrian are extracted and subjected to polarization signature analysis to determine if the pedestrian is bearing explosive devices. Low pass filtering of the of the baseband co-polarized and cross-polarized radar return signals prior to integration provides range aliasing to reject signal content associated with objects beyond the unambiguous range of the radar apparatus.

US Patent:

20190013071, Jan 10, 2019

Filed:

Jul 17, 2018

Appl. No.:

16/037255

Inventors:

- Santa Clara CA, US
Daniel Chu - Folsom CA, US
John Gorman - San Jose CA, US
Mase Taub - Folsom CA, US
Sandeep Guliani - Folsom CA, US
Kiran Pangal - Fremont CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 13/00

Abstract:

In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

US Patent:

20180190353, Jul 5, 2018

Filed:

Dec 30, 2016

Appl. No.:

15/396224

Inventors:

- Santa Clara CA, US
Daniel Chu - Folsom CA, US
John Gorman - San Jose CA, US
Mase Taub - Folsom CA, US
Sandeep Guliani - Folsom, US
Kiran Pangal - Fremont CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 13/00

Abstract:

In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.