John J Gorman

US Patent:

20110094574, Apr 28, 2011

Filed:

Dec 24, 2009

Appl. No.:

12/647201

Inventors:

Renhua Zhang - Sunnyvale CA, US
Bill Phan - San Jose CA, US
John Gorman - Los Gatos CA, US
Alain Paul Blosse - Belmont CA, US
Martin Kaes - Berlin, DE

Assignee:

Calisolar Inc. - Sunnyvale CA

International Classification:

H01L 31/00

US Classification:

136256

Abstract:

A polarization resistant solar cell is provided. The solar cell uses a dual layer dielectric stack disposed on the front surface of the cell. The dielectric stack consists of a passivation layer disposed directly on the front cell surface and comprised of either SiOor SiON, and an outer AR coating comprised of SiCN.

US Patent:

20220254999, Aug 11, 2022

Filed:

Feb 28, 2022

Appl. No.:

17/682297

Inventors:

- Santa Clara CA, US
Davide MANTEGAZZA - Palo Alto CA, US
John GORMAN - San Jose CA, US
Iniyan Soundappa ELANGO - Lehi UT, US
Davide FUGAZZA - San Jose CA, US
Andrea REDAELLI - Casatenovo, IT
Fabio PELLIZZER - Cornate d'Adda Province -MB, IT

International Classification:

H01L 45/00
H01L 27/24

Abstract:

A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.

US Patent:

20210151672, May 20, 2021

Filed:

Nov 19, 2019

Appl. No.:

16/688309

Inventors:

- Santa Clara CA, US
DAVIDE MANTEGAZZA - Palo Alto CA, US
JOHN GORMAN - San Jose CA, US
INIYAN SOUNDAPPA ELANGO - Lehi UT, US
DAVIDE FUGAZZA - San Jose CA, US
ANDREA REDAELLI - Milano, IT
FABIO PELLIZZER - Boise ID, US

Assignee:

INTEL CORPORATION - Santa Clara CA

International Classification:

H01L 45/00
H01L 27/24

Abstract:

A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.