John A Hansen

US Patent:

6741953, May 25, 2004

Filed:

Apr 10, 2002

Appl. No.:

10/119481

Inventors:

Adrian M. Hernandez - Colorado Springs CO
John David Hansen - Colorado Springs CO
John J. Sinnott - Colorado Springs CO

Assignee:

Agilent Technologies, Inc. - Palo Alto CA

International Classification:

G06F 1500

US Classification:

702187, 702 66, 714 46

Abstract:

A data acquisition circuit and method according to embodiments of the invention insert overflow states into a data storage unit among samples of input data and associated time tags that are of interest. The overflow states allow multiple overflows of the time tags without intervening samples of input data being stored, thus allowing the infrequent capture of samples of the input data while maintaining accurate timing data. Also, the overflow states obviate the need to store an overflow status flag with each stored sample of input data and time tag in the data storage unit.

US Patent:

D3614590, Aug 22, 1995

Filed:

Dec 29, 1993

Appl. No.:

D/016876

Inventors:

John A. Hansen - Sioux Falls SD

US Classification:

D 6487

US Patent:

50518887, Sep 24, 1991

Filed:

Dec 30, 1988

Appl. No.:

7/292590

Inventors:

John D. Hansen - Colorado Springs CO
Arnold S. Berger - Colorado Springs CO
Lewis S. Kootstra - Colorado Springs CO
Beth V. Jones - Colorado Springs CO
Stan W. Bowlin - Colorado Springs CO
William Fleck - Colorado Springs CO

Assignee:

Hewlett Packard Company

International Classification:

G06F 906
G06F 1516
G06F 9455
G06F 1312

US Classification:

364200

Abstract:

A system for coordinating the measurement activity of a plurality of emulators and their associated internal analyzers uses a bus with three signal lines. A READY signal is set false by any emulator that initiates a break (a transition from running user code to running a monitor). The READY signal is set false by the breaking emulator at the very beginning of its break, without waiting for the resumption of the monitor program. The false ready signal is detected immediately by the other emulators, which then break in sympathy. The READY signal is further used to restart all emulators in unsion. The emulator that initiated the break remains running its monitor, while the others start their monitors, determine that they did not cause the break, and then in anticipation of a restart, essentially suspend their monitors and prepare to start running user code. As each emulator becomes ready it releases the READY signal. As the last emulator becomes ready, it too releases READY, which then goes true.

US Patent:

43386776, Jul 6, 1982

Filed:

Jun 17, 1980

Appl. No.:

6/160262

Inventors:

Justin S. Morrill - Cascade CO
John D. Hansen - Colorado Springs CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 300
G06F 314

US Classification:

364900

Abstract:

A data capture circuit for a logic state analyzer includes a qualifier pattern comparator circuit that responds to a collection of input qualifier signals by producing a number of qualifier pattern signals each representative of the occurrence of a preselectable pattern in the input qualified signals. A like number of clock detection circuits each responds separately to the values of separate clock signals by producing separate qualified clock signals, each of the like number of which represents the simultaneous occurrence of a preselected transition in each particular clock signal and of a qualifier pattern signal associated with that clock signal. The several separate qualified clock signals generally occur at separate times, and each is used to individually capture into several temporary storage registers separate collections of data signal values occurring at those separate times. A master clock selection means allows the user to designate as a master clock signal a qualified clock signal that is expected to occur not earlier in sequence than the others. The master clock signal causes transfer of the contents of the temporary storage registers into intermediate storage registers whose outputs are then merged and combined by subsequent and simultaneous forwarding as a single parallel entity to the main data memory of the logic state analyzer, while at the same time the temporary storage registers are freed to capture fresh data.

US Patent:

52029760, Apr 13, 1993

Filed:

Jun 21, 1991

Appl. No.:

7/718728

Inventors:

John D. Hansen - Colorado Springs CO
Arnold S. Berger - Colorado Springs CO
Lewis S. Kootstra - Colorado Springs CO
Beth V. Jones - Colorado Springs CO
Stan W. Bowlin - Colorado Springs CO
William Fleck - Colorado Springs CO

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1516
G06F 900
G06F 1130

US Classification:

395500

Abstract:

A system for coordinating the measurement activity of a plurality of emulators and their associated internal analyzers uses a bus with three signal lines. A READY signal is set false by any emulator that initiates a break (a transition from running user code to running a monitor). The READY signal is set false by the breaking emulator at the very beginning of its break, without waiting for the resumption of the monitor program. The false ready signal is detected immediately by the other emulators, which then break in sympathy. The READY signal is further used to restart all emulators in unison. The emulator that initiated the break remains running its monitor, while the others start their monitors, determine that they did not cause the break, and then in anticipation of a restart, essentially suspend their monitors and prepared to start running user code. As each emulator becomes ready it releases the READY signal. As the last emulator becomes ready, it too releases READY, which then does true.

Address:

5405 S Lewis Ave, Sioux Falls, SD 57108

VIN:

1HGCM66597A018350

Make:

HONDA

Model:

ACCORD

Year:

2007