John S Hansen

US Patent:

62720406, Aug 7, 2001

Filed:

Sep 29, 2000

Appl. No.:

9/675204

Inventors:

Eric J. Salter - Scottsdale AZ
John P. Hansen - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 1100

US Classification:

365158

Abstract:

A system and method for programming a magnetoresistive memory array by applying current on a memory line aligned along the easy axis of the memory array, where the current generates a magnetic field that is independently sufficient to program at least two multi-state magnetoresistive memory elements coupled along the memory line. The memory array may be organized as one or more column memory lines along the easy axis and one or more row memory lines along a hard axis. In this configuration, the column drive circuitry includes a current source for each column memory line that is capable of programming all of the memory elements along the respective column memory line. Each column current source may assert a lesser or medium current level that generates a magnetic field that is insufficient alone to program the logic state of any memory element in the memory array. The medium current level, however, is sufficient to program each memory element along the corresponding column memory line when the memory element is also coupled along a row memory line that also receives a medium level current from a corresponding row current source. Each column current source may be one multi-state current source or may be several current sources to apply the appropriate programming current levels.

US Patent:

62259334, May 1, 2001

Filed:

Sep 29, 2000

Appl. No.:

9/675181

Inventors:

Eric J. Salter - Scottsdale AZ
John P. Hansen - Austin TX

Assignee:

Motorola, Inc. - Schaumburgk IL

International Classification:

H03M 166

US Classification:

341144

Abstract:

A digital to analog converter using a memory array of multi-state magnetoresistive memory elements in which a number of the memory elements are programmed in proportion to a received digital input. A source selectively applies a reference signal to the programmed memory elements in the memory array, and an analog output signal is developed at an output terminal that combines signals developed by each of the memory elements. The reference signal may be a voltage or current signal, where the output signal is a current or voltage signal, respectively. The memory array may include column and row drive circuitry and control logic that controls the drive circuitry to program the memory array and assert the reference signal to develop the output signal. The control logic may be configured to program the memory array in successive steps by first programming one or more complete memory lines and then programming one or more partial memory lines. Alternatively, the control logic and the drive circuitry may be configured to program the memory array in a single write operation.

US Patent:

62524712, Jun 26, 2001

Filed:

Sep 29, 2000

Appl. No.:

9/675182

Inventors:

Eric J. Salter - Scottsdale AZ
John P. Hansen - Austin TX

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H03B 100
G11C 1100

US Classification:

331179

Abstract:

A programmable oscillator including a memory array of magnetoresistive memory elements, where the memory array is programmed to any one of multiple states based on one or more values and provides an output signal that controls a variable oscillator. The variable oscillator provides a frequency signal that corresponds to the output signal. The oscillator may be a voltage controlled oscillator (VCO) where the memory array is a voltage divider receiving a voltage reference signal and having a voltage junction that asserts a control voltage to the VCO. The voltage divider may include multiple voltage dividers, each including resistive circuits coupled on either side of the voltage junction and each programmed by a corresponding value. A frequency select register stores a frequency select value to program a frequency voltage divider. A trim select register stores a trim value to program a trim voltage divider.