John N Hoang

US Patent:

54295106, Jul 4, 1995

Filed:

Dec 1, 1993

Appl. No.:

8/161282

Inventors:

William D. Barraclough - Danville CA
Mikhail A. Alperin - San Francisco CA
Jeffrey A. Brehm - So. San Francisco CA
John D. Hoang - Milpitas CA
Patrick M. Shepherd - San Jose CA
James F. Tomic - San Francisco CA

Assignee:

Aehr Test Systems, Inc. - Mountain View CA

International Classification:

H01R 909

US Classification:

439 59

Abstract:

A high density interconnect system (30) employs contact fingers (32) on both surfaces (34) and (36) of burn-in PCB (38), feed-through PCB (40) and driver PCB (42). Each of the PCBs (38), (40) and (42) has a card-edge connector (44), (46) and (48). The feed-through PCB (40) has a second card-edge connector (40) and a second set of contact fingers (32), since it mates with both the burn-in PCB (38) and the driver PCB (42). The contact fingers (32) and the card-edge connectors (44), (46), (48) and (50) of each PCB (38), (40) and (42) mate inversely with each other on adjacent PCBs, i. e. , the card-edge connector (44) of the burn-in PCB (38) mates with the contact fingers (32) of the feed-through PCB (40), and the card-edge connector (46) of the feed-through PCB (40) mates with the contact fingers (32) of the burn-in PCB (38), for example. The same relationship exists between the card-edge connector (50) of the feed-through PCB (40), the card-edge connector (48) of the driver PCB (42) and the contact fingers (32) of the feed-through PCB(40) and the driver PCB (42).

US Patent:

20210391355, Dec 16, 2021

Filed:

Oct 22, 2019

Appl. No.:

17/283645

Inventors:

- Fremont CA, US
Meihua SHEN - Fremont CA, US
John HOANG - Fremont CA, US
Hui-Jung WU - Pleasanton CA, US
Gereng GUNAWAN - Saratoga CA, US
Yang PAN - Los Altos CA, US

International Classification:

H01L 27/11582
H01L 27/11519
H01L 27/11556
H01L 27/11565
H01L 27/11587
H01L 27/11597

Abstract:

A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.

US Patent:

20160104630, Apr 14, 2016

Filed:

Dec 22, 2014

Appl. No.:

14/579822

Inventors:

- Fremont CA, US
Ji ZHU - Castro Valley CA, US
Shuogang HUANG - San Jose CA, US
Baosuo ZHOU - Redwood City CA, US
John HOANG - Fremont CA, US
Prithu SHARMA - Santa Clara CA, US
Thorsten LILL - Santa Clara CA, US

International Classification:

H01L 21/3213
H01L 21/768

Abstract:

A method of opening a barrier film below copper structures in a stack is provided. A pulsed gas is provided into a plasma processing chamber, wherein the providing the pulsed gas comprises providing a pulsed Hcontaining gas and providing a pulsed halogen containing gas, wherein the pulsed Hcontaining gas and the pulsed halogen containing gas are pulsed out of phase, and wherein the pulsed Hcontaining gas has an Hhigh flow period and the pulsed halogen containing gas has a halogen containing gas high flow period, wherein the Hhigh flow period is greater than the halogen containing gas high flow period. The pulsed gas is formed into a plasma. The copper structures and the barrier film are exposed to the plasma, which etches the barrier film. In another embodiment, a wet and dry cyclical process may be used.

US Patent:

20150249016, Sep 3, 2015

Filed:

Jul 22, 2014

Appl. No.:

14/337953

Inventors:

- Fremont CA, US
Gowri Kamarthy - Pleasanton CA, US
Harmeet Singh - Fremont CA, US
Yoshie Kimura - Castro Valley CA, US
Meihua Shen - Fremont CA, US
Baosuo Zhou - Redwood City CA, US
Yifeng Zhou - Fremont CA, US
John Hoang - Fremont CA, US

International Classification:

H01L 21/3065
H01L 21/66
H01L 21/67
H01L 21/306
H01L 21/02

Abstract:

A method of planarizing an upper surface of a semiconductor substrate in a plasma etch chamber comprises supporting the substrate on a support surface of a substrate support assembly that includes an array of independently controlled thermal control elements therein which are operable to control the spatial and temporal temperature of the support surface of the substrate support assembly to form independently controllable heater zones which are formed to correspond to a desired temperature profile across the upper surface of the semiconductor substrate. The etch rate across the upper surface of the semiconductor substrate during plasma etching depends on a localized temperature thereof wherein the desired temperature profile is determined such that the upper surface of the semiconductor substrate is planarized within a predetermined time. The substrate is plasma etched for the predetermined time thereby planarizing the upper surface of the substrate.