John Dinh Hoang

US Patent:

6562636, May 13, 2003

Filed:

Jul 14, 1999

Appl. No.:

09/353121

Inventors:

John Dinh Hoang - San Jose CA
Jerry Lobacz - San Mateo CA

Assignee:

Aehr Test Systems - Fremont CA

International Classification:

H01L 2166

US Classification:

438 14, 438 15, 438 16, 438 17, 324760

Abstract:

A burn-in and electrical test system ( ) includes a temperature controlled zone ( ) and a cool zone ( ) separated by a transition zone The temperature controlled zone ( ) is configured to receive a plurality of wafer cartridges ( ) and connect the cartridges ( ) to test electronics ( ) and power electronics ( ), which are mounted in the cool zone ( ). Each of the wafer cartridges ( ) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics ( ) consists of a pattern generator PCB ( ) and a signal driver and fault analysis PCB ( ) connected together by a parallel bus ( ). The pattern generator PCB ( ) and the fault analysis PCB ( ) are connected to a rigid signal probe PCB ( ) in cartridge ( ) to provide a straight through signal path. The probe PCB ( ) is rigid in order to allow close control of capacitance between each signal line and a backplane, thus providing impedance controlled interconnections between a semiconductor wafer under test and the test electronics ( ). The power distribution system ( ) is connected to a probe power PCB ( ) in the cartridge ( ).

US Patent:

6682945, Jan 27, 2004

Filed:

May 25, 2001

Appl. No.:

09/865957

Inventors:

John Dinh Hoang - San Jose CA
Jerzy Lobacz - San Mateo CA

Assignee:

AEHR Test Systems - Fremont CA

International Classification:

H01L 2166

US Classification:

438 14, 438 15, 324758

Abstract:

A burn-in and electrical test system ( ) includes a temperature controlled zone ( ) and a cool zone ( ) separated by a transition zone The temperature controlled zone ( ) is configured to receive a plurality of wafer cartridges ( ) and connect the cartridges ( ) to test electronics ( ) and power electronics ( ), which are mounted in the cool zone ( ). Each of the wafer cartridges ( ) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics ( ) consists of a pattern generator PCB ( ) and a signal driver and fault analysis PCB ( ) connected together by a parallel bus ( ). The pattern generator PCB ( ) and the fault analysis PCB ( ) are connected to a rigid signal probe PCB ( ) in cartridge ( ) to provide a straight through signal path. The probe PCB ( ) is rigid in order to allow close control of capacitance between each signal line and a backplane, thus providing impedance controlled interconnections between a semiconductor wafer under test and the test electronics ( ). The power distribution system ( ) is connected to a probe power PCB ( ) in the cartridge ( ).

US Patent:

7619428, Nov 17, 2009

Filed:

Nov 21, 2003

Appl. No.:

10/718825

Inventors:

John Dinh Hoang - San Jose CA, US
Jerzy Lobacz - San Mateo CA, US

Assignee:

Aehr Test Systems - Fremont CA

International Classification:

G01R 31/02

US Classification:

324760, 438 14

Abstract:

A burn-in and electrical test system () includes a temperature controlled zone () and a cool zone () separated by a transition zone. The temperature controlled zone () is configured to receive a plurality of wafer cartridges () and connect the cartridges () to test electronics () and power electronics (), which are mounted in the cool zone (). Each of the wafer cartridges () contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics () consists of a pattern generator PCB () and a signal driver and fault analysis PCB () connected together by a parallel bus (). The pattern generator PCB () and the fault analysis PCB () are connected to a rigid signal probe PCB () in cartridge () to provide a straight through signal path. The probe PCB () is rigid in order to allow close control of capacitance between each signal line and a backplane, thus providing impedance controlled interconnections between a semiconductor wafer under test and the test electronics (). The power distribution system () is connected to a probe power PCB () in the cartridge ().

US Patent:

7928754, Apr 19, 2011

Filed:

Oct 6, 2009

Appl. No.:

12/574447

Inventors:

John Dinh Hoang - San Jose CA, US
Jerzy Lobacz - San Mateo CA, US

Assignee:

Aehr Test Systems - Fremont CA

International Classification:

G01R 31/02

US Classification:

32476205, 32475005

Abstract:

A burn-in and electrical test system () includes a temperature controlled zone () and a cool zone () separated by a transition zone. The temperature controlled zone () is configured to receive a plurality of wafer cartridges () and connect the cartridges () to test electronics () and power electronics (), which are mounted in the cool zone (). Each of the wafer cartridges () contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics () consists of a pattern generator PCB () and a signal driver and fault analysis PCB () connected together by a parallel bus (). The pattern generator PCB () and the fault analysis PCB () are connected to a rigid signal probe PCB () in cartridge () to provide a straight through signal path. The probe PCB () is rigid in order to allow close control of capacitance between each signal line and a backplane, thus providing impedance controlled interconnections between a semiconductor wafer under test and the test electronics (). The power distribution system () is connected to a probe power PCB () in the cartridge ().

US Patent:

54295106, Jul 4, 1995

Filed:

Dec 1, 1993

Appl. No.:

8/161282

Inventors:

William D. Barraclough - Danville CA
Mikhail A. Alperin - San Francisco CA
Jeffrey A. Brehm - So. San Francisco CA
John D. Hoang - Milpitas CA
Patrick M. Shepherd - San Jose CA
James F. Tomic - San Francisco CA

Assignee:

Aehr Test Systems, Inc. - Mountain View CA

International Classification:

H01R 909

US Classification:

439 59

Abstract:

A high density interconnect system (30) employs contact fingers (32) on both surfaces (34) and (36) of burn-in PCB (38), feed-through PCB (40) and driver PCB (42). Each of the PCBs (38), (40) and (42) has a card-edge connector (44), (46) and (48). The feed-through PCB (40) has a second card-edge connector (40) and a second set of contact fingers (32), since it mates with both the burn-in PCB (38) and the driver PCB (42). The contact fingers (32) and the card-edge connectors (44), (46), (48) and (50) of each PCB (38), (40) and (42) mate inversely with each other on adjacent PCBs, i. e. , the card-edge connector (44) of the burn-in PCB (38) mates with the contact fingers (32) of the feed-through PCB (40), and the card-edge connector (46) of the feed-through PCB (40) mates with the contact fingers (32) of the burn-in PCB (38), for example. The same relationship exists between the card-edge connector (50) of the feed-through PCB (40), the card-edge connector (48) of the driver PCB (42) and the contact fingers (32) of the feed-through PCB(40) and the driver PCB (42).

US Patent:

20210391355, Dec 16, 2021

Filed:

Oct 22, 2019

Appl. No.:

17/283645

Inventors:

- Fremont CA, US
Meihua SHEN - Fremont CA, US
John HOANG - Fremont CA, US
Hui-Jung WU - Pleasanton CA, US
Gereng GUNAWAN - Saratoga CA, US
Yang PAN - Los Altos CA, US

International Classification:

H01L 27/11582
H01L 27/11519
H01L 27/11556
H01L 27/11565
H01L 27/11587
H01L 27/11597

Abstract:

A three-dimensional (3D) memory structure includes memory cells and a plurality of oxide layers and a plurality of word line layers. The plurality of oxide layers and the plurality of word line layers are alternately stacked in a first direction. A plurality of double channel holes extend through the plurality of oxide layers and the plurality of word line layers in the first direction. The plurality of double channel holes have a peanut-shaped cross-section in a second direction that is transverse to the first direction.

US Patent:

20180102236, Apr 12, 2018

Filed:

Nov 28, 2017

Appl. No.:

15/824987

Inventors:

- Fremont CA, US
Baosuo Zhou - Redwood City CA, US
Meihua Shen - Fremont CA, US
Thorsten Lill - Santa Clara CA, US
John Hoang - Fremont CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01J 37/32
H01L 21/3213

Abstract:

Methods of etching cobalt on substrates are provided. Some methods involve exposing the substrate to a boron-containing halide gas and an additive, and exposing the substrate to an activation gas and a plasma. Additives improve selectively depositing a thicker layer of a boron-containing halide material on a surface of a mask than on a surface of a metal. Additives include H, CH, CF, NF, and Cl. Boron-containing halide gases include BCl, BBr, BF, and Bl. Exposures may be performed in two or more cycles, with variations in durations and/or bias power for each exposure in the two or more cycles.

US Patent:

20160314985, Oct 27, 2016

Filed:

Jun 24, 2015

Appl. No.:

14/749285

Inventors:

- Fremont CA, US
Baosuo Zhou - Redwood City CA, US
Meihua Shen - Fremont CA, US
Thorsten Lill - Santa Clara CA, US
John Hoang - Fremont CA, US

International Classification:

H01L 21/3065
H01L 21/308

Abstract:

Methods of etching cobalt on substrates are provided. Some methods involve exposing the substrate to a boron-containing halide gas and an additive, and exposing the substrate to an activation gas and a plasma. Additives improve selectively depositing a thicker layer of a boron-containing halide material on a surface of a mask than on a surface of a metal. Additives include H, CH, CF, NF, and Cl. Boron-containing halide gases include BCl, BBr, BF, and BI. Exposures may be performed in two or more cycles, with variations in durations and/or bias power for each exposure in the two or more cycles.