John T Kolias

US Patent:

53846907, Jan 24, 1995

Filed:

Jul 27, 1993

Appl. No.:

8/097544

Inventors:

Charles R. Davis - Endicott NY
Thomas P. Duffy - Endicott NY
Steven L. Hanakovic - Vestal NY
Howard L. Heck - Endcott NY
John T. Kolias - Vestal NY
John S. Kresge - Binghamton NY
David N. Light - Friendsville PA
Ajit K. Trivedi - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01R 2368

US Classification:

361789

Abstract:

Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate.

US Patent:

56207824, Apr 15, 1997

Filed:

Jun 2, 1995

Appl. No.:

8/459929

Inventors:

Charles R. Davis - Endicott NY
Thomas P. Duffy - Endicott NY
Steven L. Hanakovic - Vestal NY
Howard L. Heck - Endcott NY
John T. Kolias - Vestal NY
John S. Kresge - Binghamton NY
David N. Light - Friendsville PA
Ajit K. Trivedi - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

B32B 900

US Classification:

428209

Abstract:

Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate.

US Patent:

55091962, Apr 23, 1996

Filed:

Sep 21, 1994

Appl. No.:

8/310190

Inventors:

Charles R. Davis - Endicott NY
Thomas P. Duffy - Endicott NY
Steven L. Hanakovic - Vestal NY
Howard L. Heck - Endcott NY
John T. Kolias - Vestal NY
John S. Kresge - Binghamton NY
David N. Light - Friendsville PA
Ajit K. Trivedi - Endicott NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H05K 336
H05K 320

US Classification:

29830

Abstract:

Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. Lamination of the individual subassemblies is accomplished with a low melting adhesive that is chemical compatible with (bondable to) the perfluorocarbon polymer between the subassemblies in the regions intended to be laminated, and, optionally, a high melting mask that is chemically incompatible with (not bondable to) the perfluorocarbon polymer between the subassemblies in the regions not intended to be laminated. The subassembly stack is heated to selectively effect adhesion and lamination in areas thereof intended to be laminated while avoiding lamination in areas not intended to be laminated.

Address:

2722 Maitland Dr, Ann Arbor, MI 48105

Phone:

7343694554

VIN:

3FAHP0JG0CR434519

Make:

FORD

Model:

FUSION

Year:

2012