John E Kunz

US Patent:

8191027, May 29, 2012

Filed:

Oct 4, 2007

Appl. No.:

11/867012

Inventors:

Vrashank Gurudatta Shukla - Bangalore, IN
James Garrett Homack - Dallas TX, US
John Eric Kunz - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 17/50

US Classification:

716132, 716115, 716136

Abstract:

An aspect of the present invention validates ESD compliance by examining netlist data generated from a schematic level design of an integrated circuit. Routing and placement may be performed only after confirming that whether each protected circuit (having exposure to ESD current, without the protection circuit) is protected by an appropriate protection circuit. As a result, the design cycle time may be reduced. According to another aspect of the present invention, layout guidelines for each protection circuit is also considered in performing the routing and placement. As a result, the number of iterations in a design cycle may be reduced.

US Patent:

20050104613, May 19, 2005

Filed:

Jun 17, 2004

Appl. No.:

10/870773

Inventors:

Charvaka Duvvury - Plano TX, US
John Kunz - Allen TX, US
Robert Steinhoff - Dallas TX, US

International Classification:

G01R031/26

US Classification:

324765000, 361765000

Abstract:

An equipment () for testing semiconductor device performance under high energy pulse conditions, which comprises a high voltage generator () and an on/off switch relay (). The relay is resistively connected by a first resistor () to the generator and by a second resistor () to the socket () for the device-under-test (); the relay is operable in a partially ionized ambient. A capacitor () is connected to the relay, to the generator, and to the device, and is operable to discharge high energy pulses through the device. A third resistor () is in parallel with the capacitor and the device, and is operable to suppress spurious pulses generated by the relay. This third resistor has a value between about 1 kΩ and 1 MΩ, preferably about 10 kΩ, several orders of magnitude greater than the on-resistance of the device-under-test.

US Patent:

20060231895, Oct 19, 2006

Filed:

Jun 17, 2005

Appl. No.:

11/155062

Inventors:

Charvaka Duvvury - Plano TX, US
Gianluca Boselli - Richardson TX, US
John Kunz - Allen TX, US

International Classification:

H01L 23/62

US Classification:

257355000

Abstract:

A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor () in a first n-well () having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact () to the first n-well, which touches source junction . Source has further an ohmic (silicided) connection to contact . A finger-shaped diode () with its cathode () is located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well () positioned between the first n-well and the diode, the third n-well connected to power (Vdd) and approximately perpendicular to the first n-well contact, acting as a guard wall ().

US Patent:

20060231897, Oct 19, 2006

Filed:

Apr 15, 2005

Appl. No.:

11/107033

Inventors:

Charvaka Duvvury - Plano TX, US
Gianluca Boselli - Richardson TX, US
John Kunz - Allen TX, US

International Classification:

H01L 29/76

US Classification:

257356000, 257374000, 257360000

Abstract:

A semiconductor circuit for protecting an I/O pad against ESD events comprising a pMOS transistor () in a first n-well () having its source connected to Vdd and the first n-well, and its drain connected to the I/O pad; the transistor has a finger-shaped contact () to the first n-well. Further a finger-shaped diode () with its cathode () located in a second n-well and connected to the I/O pad, and its anode connected to ground. The anode is positioned between the cathode and the first n-well, whereby the finger-shaped anode and cathode are oriented approximately perpendicular to the finger-shaped transistor n-well contact. Further a third finger-shaped n-well () positioned between the first n-well and the diode, the third n-well connected to ground and approximately perpendicular to the first n-well contact, acting as a guard wall ().