John J Lambe

US Patent:

48766682, Oct 24, 1989

Filed:

Apr 29, 1986

Appl. No.:

6/857076

Inventors:

Anilkumar P. Thakoor - Pasadena CA
John Lambe - Altadena CA
Alexander Moopen - Pasadena CA

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

G11C 1300

US Classification:

365163

Abstract:

Memory cells in a matrix are provided by a thin film of amorphous semiconductor material overlayed by a thin film of resistive material. An array of parallel conductors on one side perpendicular to an array of parallel conductors on the other side enable the amorphous semiconductor material to be switched in addressed areas to be switched from a high resistance state to a low resistance state with a predetermined level of electrical energy applied through selected conductors, and thereafter to be read out with a lower level of electrical energy. Each cell may be fabricated in the channel of an MIS field-effect transistor with a separate common gate over each section to enable the memory matrix to be selectively blanked in sections during storing or reading out of data. This allows for time sharing of addressing circuitry for storing and reading out data in a synaptic network, which may be under control of a microprocessor.

US Patent:

49690213, Nov 6, 1990

Filed:

Jun 12, 1989

Appl. No.:

7/364114

Inventors:

Anilkumar P. Thakoor - Pasadena CA
Alexander W. Moopenn - Pasadena CA
John J. Lambe - Redmond WA

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

H01L 2978

US Classification:

357 235

Abstract:

An electrically programmable, erasable, read-only memory is comprised of an array of vertical porous floating gate MOSFET structures in a layer of a-Si with parallel X and parallel Y conductors on opposite sides of the a-Si layer functioning as source and drain electrodes. The floating gate of each vertical MOSFET structure consists of a plurality of electrically insulated metallic particles embedded in the a-Si layer between said source and said drain electrodes with the metallic particles adjacent to the source electrodes. The insulation between the metallic particles and the a-Si material is thick enough to prevent tunneling of electrons but the insulation between the particles and the source electrode is thinner to allow tunneling of electrons at a predetermined threshold voltage to store a charge in the porous floating gate. Alternatively, the metal particles may be gathered into one insulated toroidal gate which controls current through a-Si in the center of the toroidal gate. Analog or binary information may be stored in the vertical MOSFET structures by application of high voltage.

US Patent:

47288515, Mar 1, 1988

Filed:

Jan 8, 1982

Appl. No.:

6/338463

Inventors:

John J. Lambe - Altadena CA

Assignee:

Ford Motor Company - Dearborn MI

International Classification:

H01J 102

US Classification:

313309

Abstract:

A field emitter device utilizing a gate electrode adjacent a carbon fiber electron emitter cathode for controlling the initial flow of electrons between the cathode and a collector element. Subsequent disconnect of the gate electrode from its power source does not affect the electron flow and thereby provides a bistable memory type device. Luminescent material on the collector provides a light emission display at points corresponding to electron flow between the emitter and the collector.

US Patent:

49317636, Jun 5, 1990

Filed:

Feb 16, 1988

Appl. No.:

7/157318

Inventors:

Anilkumar P. Thakoor - Pasadena CA
John J. Lambe - Redmond WA

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

H01C 710
H01C 1012

US Classification:

338 22SD

Abstract:

MnO. sub. 2-x thin films (12) exhibit irreversible memory switching (28) with an "OFF/ON" resistance ratio of at least about 10. sup. 3 and the tailorability of "ON" state (20) resistance. Such films are potentially extremely useful as a "connection" element in a variety of microelectronic circuits and arrays (24). Such films provide a pre-tailored, finite, non-volatile resistive element at a desired place in an electric circuit, which can be electrically turned OFF (22) or "disconnected" as desired, by application of an electrical pulse. Microswitch structures (10) constitute the thin film element, contacted by a pair of separate electrodes (16a, 16b) and have a finite, pre-selected ON resistance which is ideally suited, for example, as a programmable binary synaptic connection for electronic implementation of neural network architectures. The MnO. sub. 2-x microswitch is non-volatile, patternable, insensitive to ultraviolet light, and adherent to a variety of insulating substrates (14), such as glass and silicon dioxide-coated silicon substrates.

US Patent:

48071684, Feb 21, 1989

Filed:

Jun 10, 1987

Appl. No.:

7/060201

Inventors:

Alexander W. Moopenn - Pasadena CA
Anilkumar P. Thakoor - Pasadena CA
John J. Lambe - Redmond WA

Assignee:

The United States of America as represented by the Administrator,
National Aeronautics and Space Administration - Washington DC

International Classification:

G06J 100
G06G 712
G06G 7122
G11C 1504

US Classification:

364602

Abstract:

Random access memory is used to store synaptic information in the form of a matrix of rows and columns of binary digits. N rows read in sequence are processed through switches and resistors, and a summing amplifier to N neural amplifiers in sequence, one row for each amplifier, using a first array of sample-and-hold devices S/H1 for commutation. The outputs of the neural amplifiers are stored in a second array of sample-and-hold devices S/H2 so that after N rows are processed, all of said second array of sample-and-hold devices are updated. A second memory may be added for binary values of 0 and -1, and processed simultaneously with the first to provide for values of 1, 0, and -1, the results of which are combined in a difference amplifier.

US Patent:

48398594, Jun 13, 1989

Filed:

Dec 4, 1987

Appl. No.:

7/128872

Inventors:

Alexander W. Moopenn - Pasadena CA
Anilkumar P. Thakoor - Pasadena CA
Taher Daud - La Crescenta CA
John J. Lambe - Redmond WA

Assignee:

The California Institute of Technology - Pasadena CA

International Classification:

G11C 1100

US Classification:

365100

Abstract:

A multi-layered, thin-film, digital memory having associative recall. There is a first memory matrix and a second memory matrix. Each memory matrix comprises, a first layer comprising a plurality of electrically separated row conductors; a second layer comprising a plurality of electrically separated column conductors intersecting but electrically separated from the row conductors; and, a plurality of resistance elements electrically connected between the row condutors and the column conductors at respective intersections of the row conductors and the column conductors, each resistance element comprising, in series, a first resistor of sufficiently high ohmage to conduct a sensible element current therethrough with virtually no heat-generating power consumption when a low voltage as employed in thin-film applications is applied thereacross and a second resistor of sufficiently high ohmage to conduct no sensible current therethrough when a low voltage as employed in thin-film applications is applied thereacross, the second resistor having the quality of breaking down to create a short therethrough upon the application of a breakdown level voltage across the first and second resistors.